bldc_motor_control_design_example

代码说明：

  无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA( actel VERILOG BLDC control of the use of actel FPGA)

文件列表：

Application Note Disclaimer.doc,26112,2009-08-06
bldc_ip
.......\bldc_ip_libero_project.prj,7484,2008-05-10
.......\component
.......\constraint
.......\coreconsole
.......\designer
.......\........\impl1
.......\........\.....\designer.log,602,2008-05-10
.......\........\.....\simulation
.......\........\.....\top_bldc_ip.adb,399360,2008-05-10
.......\........\.....\top_bldc_ip.dtf
.......\........\.....\...............\verify.log,233,2008-05-10
.......\........\.....\top_bldc_ip.ide_des,657,2008-05-10
.......\........\.....\top_bldc_ip.stp,76192,2008-05-10
.......\........\.....\top_bldc_ip.tcl,177,2008-05-10
.......\hdl
.......\...\baud_clk_gen.v,1141,2008-05-10
.......\...\bdbl_driver.v,11158,2008-05-10
.......\...\bd_bl_speedcontrol.v,4443,2008-05-10
.......\...\bldc_ip.v,4182,2008-05-10
.......\...\clkdiv_20M_to_10M.v,457,2008-05-10
.......\...\clk_by_2.v,848,2008-05-10
.......\...\clk_gen.v,4420,2008-05-10
.......\...\debounce.v,1464,2008-05-10
.......\...\debounce_blk.v,1679,2008-05-10
.......\...\divideby5.v,948,2008-05-10
.......\...\div_by_16.v,986,2008-05-10
.......\...\global.v,489,2008-05-10
.......\...\mux_hw_sw.v,3376,2008-05-10
.......\...\PLL20_to_10.v,2462,2008-05-06
.......\...\pwm_gen_bdbl.v,2754,2008-05-10
.......\...\recv_control.v,8796,2008-05-10
.......\...\serial.v,11683,2008-05-10
.......\...\top_bldc.v,3227,2008-05-10
.......\...\top_bldc_ip.v,6258,2008-05-10
.......\...\top_serial.v,3091,2008-05-10
.......\...\xmit_control.v,3642,2008-05-10
.......\phy_synthesis
.......\Readme_bldc_ip_project.txt,1530,2009-08-06
.......\simulation
.......\..........\modelsim.ini,294,2008-05-10
.......\..........\modelsim.ini.sav,292,2008-05-10
.......\..........\modelsim.log,4325,2008-05-10
.......\..........\presynth
.......\..........\........\baud_clk_gen
.......\..........\........\............\verilog.psm,8495,2008-05-10
.......\..........\........\............\_primary.dat,762,2008-05-10
.......\..........\........\............\_primary.dbs,2045,2008-05-10
.......\..........\........\............\_primary.vhd,229,2008-05-10
.......\..........\........\bdbl_driver
.......\..........\........\...........\verilog.psm,42299,2008-05-10
.......\..........\........\...........\_primary.dat,6560,2008-05-10
.......\..........\........\...........\_primary.dbs,8261,2008-05-10
.......\..........\........\...........\_primary.vhd,934,2008-05-10
.......\..........\........\bd_bl_speedcontrol
.......\..........\........\..................\verilog.psm,20412,2008-05-10
.......\..........\........\..................\_primary.dat,1878,2008-05-10
.......\..........\........\..................\_primary.dbs,3601,2008-05-10
.......\..........\........\..................\_primary.vhd,582,2008-05-10
.......\..........\........\bldc_ip
.......\..........\........\.......\verilog.psm,17423,2008-05-10
.......\..........\........\.......\_primary.dat,2198,2008-05-10
.......\..........\........\.......\_primary.dbs,3491,2008-05-10
.......\..........\........\.......\_primary.vhd,1184,2008-05-10
.......\..........\........\clkdiv_20@m_to_10@m
.......\..........\........\...................\verilog.psm,2257,2008-05-10
.......\..........\........\...................\_primary.dat,247,2008-05-10
.......\..........\........\...................\_primary.dbs,410,2008-05-10
.......\..........\........\...................\_primary.vhd,239,2008-05-10
.......\..........\........\clk_by_2
.......\..........\........\........\verilog.psm,4015,2008-05-10
.......\..........\........\........\_primary.dat,355,2008-05-10
.......\..........\........\........\_primary.dbs,675,2008-05-10
.......\..........\........\........\_primary.vhd,264,2008-05-10
.......\..........\........\clk_gen
.......\..........\........\.......\verilog.psm,30508,2008-05-10
.......\..........\........\.......\_primary.dat,2387,2008-05-10
.......\..........\........\.......\_primary.dbs,7269,2008-05-10
.......\..........\........\.......\_primary.vhd,864,2008-05-10
.......\..........\........\debounce
.......\..........\........\........\verilog.psm,7490,2008-05-10
.......\..........\........\........\_primary.dat,704,2008-05-10
.......\..........\........\........\_primary.dbs,1405,2008-05-10
.......\..........\........\........\_primary.vhd,307,2008-05-10
.......\..........\........\debounce_blk
.......\..........\........\............\verilog.psm,6881,2008-05-10
.......\..........\........\............\_primary.dat,1163,2008-05-10
.......\..........\........\............\_primary.dbs,1793,2008-05-10
.......\..........\........\............\_primary.vhd,746,2008-05-10
.......\..........\........\divideby5
.......\..........\........\.........\verilog.psm,9092,2008-05-10
.......\..........\........\.........\_primary.dat,717,2008-05-10
.......\..........\........\.........\_primary.dbs,1833,2008-05-10
.......\..........\........\.........\_primary.vhd,223,2008-05-10
.......\..........\........\div_by_16
.......\..........\........\.........\verilog.psm,5286,2008-05-10
.......\..........\........\.........\_primary.dat,579,2008-05-10
.......\..........\........\.........\_primary.dbs,816,2008-05-10
.......\..........\........\.........\_primary.vhd,266,2008-05-10