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msp430x41x
低电源电压范围为1.8 V至3.6 V
超低功耗:
- 主动模式:280μA,在1 MHz,2.2伏
- 待机模式:1.1μA
- 关闭模式(RAM保持):0.1μA
五省电模式
欠待机模式唤醒
超过6微秒
16位RISC架构,
125 ns指令周期时间
12位A/ D转换器具有内部
参考,采样和保持,并
AutoScan功能
16位Timer_B随着三† 或七‡
捕捉/比较随着阴影寄存器
具有三个16位定时器A
捕捉/比较寄存器
片上比较器
串行通信接口(USART),
选择异步UART或
同步SPI软件:
- 两个USART(USART0 USART1)的†
- 一个USART(USART0)‡
掉电检测
电源电压监控器/监视器
可编程电平检测
串行板载编程,
无需外部编程电压
安全可编程代码保护
融合(Low Supply-Voltage Range, 1.8 V to 3.6 V
Ultralow-Power Consumption:
− Active Mode: 280 µ A at 1 MHz, 2.2 V
− Standby Mode: 1.1 µ A
− Off Mode (RAM Retention): 0.1 µ A
Five Power Saving Modes
Wake-Up From Standby Mode in Less
Than 6 µ s
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
16-Bit Timer_B With Three† or Seven‡
Capture/Compare-With-Shadow Registers
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1)†
− One USART (USART0)‡
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse)
- 2012-05-31 15:26:33下载
- 积分:1
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verilog实现基于i2s协议接口 i2s_interface
verilog实现基于i2s协议接口,在fpga上验证通过。(Verilog implements the interface based on I2S protocol and verifies it on fpga.)
- 2017-11-05 17:26:39下载
- 积分:1
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fpga_dsp_simple
dsp和fpag通信的测试程序,包含整个工程和signaltap测试信号。(the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.)
- 2013-04-14 15:17:20下载
- 积分:1
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dspafpga
dsp与fpga通信的verilog程序,强烈推荐欢迎参考(dsp and fpga verilog communication program, it is strongly recommended to welcome reference)
- 2020-12-04 15:59:23下载
- 积分:1
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DDS_DAC_Output
说明: 本工程使用A7系列FPGA产生DDS,用DAC0832进行正弦电压输出(In this project, A7 series FPGA is used to generate DDS, and DAC0832 is used for sinusoidal voltage output)
- 2019-05-06 10:05:10下载
- 积分:1
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FPGA NIOS II W5500
Altera FPGA NIOS II 通过W5500芯片完成网络TCP/IP通讯。
- 2022-08-10 04:58:17下载
- 积分:1
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用于FPGA的huffman算法的HDL编码
用于FPGA的huffman算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。(The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.)
- 2008-08-01 17:25:44下载
- 积分:1
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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器,分别记录在时钟上升沿时A,B,C,D的输入情况,比如某上升沿输入A,相应时刻A对应的移位寄存器输入1,其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样,密码锁不仅可以识别字符数量,还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分:1
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openmips
一个开源mips处理器verilog 源码(wishbone interface wishbone interface)
- 2020-08-16 15:48:32下载
- 积分:1
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DDR2芯片控制模块verilog
ddr2存储器控制模块,大家可以拿去借鉴,其中对DDR2内部时钟刷新本人花了很久的时间。内部时钟频率请各位已经自己芯片情况而定。本人也是新手,代码中有不少地方也许欠妥,大家共同学习,谢谢。
- 2022-02-13 11:55:09下载
- 积分:1