说明：  this file describes the steps in building a fifo buffer module in verilog hdl and programming them on an fpga device

通过UART进行的低功耗低成本的数据传输TEQ再检查一下它，一旦它的writen用Verilog语言而且它是基于一个协议，你要指定更好的沟通自己的规则

从MIC输入一段音频然后，再从AOUT的接口播放出来的verilog 的代码-Input from the MIC for some audio and then AOUT interface from broadcast in the Verilog code

说明：  使用Verilog HDL ，FM调制信号。(Using Verilog, HDL, and FM modulation signals.)

基于FPGA的电子密码锁设计-已在开发板上成功运行，通过老师检验。(FPGA based electronic password lock design- has been successfully developed on the development board, through the teacher inspection.)

NiosII_Exercises_Ver3,this niosII 3.o for cyclone

Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated

设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述，给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)

Five day stmicroelectornics vhdl training presentation

此代码实现4人表决功能，4人中有三人同意即为通过。(Four voting)