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div_fru
介绍分频器的好资料。不光有奇数分频、偶数分频，还有小数分频。相信把这个资料理解透了后以后分频器的设计就不是问题了。(Introduction divider good information. Not only have an odd frequency, even frequency, there are fractional. I believe understanding this information through the post after the Divider is not a problem.)
- 2010-06-17 21:52:55下载
- 积分：1
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DS28E01
用verilog语言实现加密芯片DS28E01的调用操作命令。(Using Verilog language to achieve the encryption chip DS28E01 call operation commands.)
- 2021-03-17 09:49:21下载
- 积分：1
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chuankou
本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分：1
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查找序列序列中两个相邻1之间的最大间隔
设计一个能求出一个1之间最大间隙的时序状态机。完成testbench描述，给出综合后的时序仿真结果
- 2022-03-15 04:42:42下载
- 积分：1
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MB
说明： 基于VHDL语言数字秒表设计,在FPGA实验平台下开发(Digital stopwatch design based on VHDL, FPGA experimental platform under development)
- 2015-04-21 20:11:14下载
- 积分：1
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sobel_filter_zx1809_v10
说明： 图像边缘检测，图像中值滤波和MATLAB处理(Digital Image processing based on FPGA)
- 2019-05-22 13:46:59下载
- 积分：1
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verilog HDL
说明： DS18B20温度模块，LCD1602显示(DS18B20 Temperature Module, LCD1602 Display)
- 2020-09-04 15:08:06下载
- 积分：1
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uart
Verilog UART is written in this file
- 2013-04-16 12:34:05下载
- 积分：1
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clock
本程序实现数字钟系统，有整点报时功能，可显示切换年月日，定时功能(Digital clock system of this program, with the whole point timekeeping function, can display the date, the timing function)
- 2015-04-19 22:07:02下载
- 积分：1
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FIFO_Buffer(verilog)
这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)
- 2021-04-22 13:38:49下载
- 积分：1
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