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verilog___UART
Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)
- 2012-05-24 20:38:27下载
- 积分:1
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vhdlcoder
VDHL的简单DEMO演示,有利于初学者学习使用(VDHL simple demo DEMO will help beginners learn to use)
- 2008-01-16 15:44:44下载
- 积分:1
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urisc
自己用verilog编写的urisc程序,调试成功,压缩包里有仿真图像,值得学习参考。(Written in verilog urisc program debugging, simulation image compression bag, worth learning reference.)
- 2021-04-22 17:38:48下载
- 积分:1
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黑金Alinx开发板DDR2读写控制器
应用背景该工程为黑金Alinx开发板配套项目,实现了实时视频采集与处理,代码架构完整清晰,非常适合视频处理算法的移植。关键技术该工程主要完成PAL制视频BT656格式的解码,视频数据DDR2存取,双线性插值放大及VGA输出,值得希望学习Altera ddr2 ip的同学参考借鉴~
- 2022-04-28 23:42:59下载
- 积分:1
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pingpang_ram
乒乓RAM静态随机存储器的控制,用于解决数据流连续存储问题。(Ping pong RAM static random access control, to solve the problem of continuous data flow storage.)
- 2020-09-22 10:17:50下载
- 积分:1
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FPGA COMS传感器接口 LCD 移动终端源代码
用FPGA实现COMS传感器接入,LCD控制,及与ARM通信的源代码,包含matlab仿真及硬件原理图和手册,非常全面
- 2022-12-10 20:50:03下载
- 积分:1
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gmsk
产生高斯最小相移键控信号的阐述仿真,包括调制解调、信道模型等。(Simulation program to realize GMSK transmission system)
- 2020-11-14 19:49:42下载
- 积分:1
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xiaomi
新版 小米抢购器 -源码
已经测试,代码很有用,已经抢了好几个小米3了,希望对大家有用(The new millet to snap up- source
Have test, the code is useful, has robbed several millet 3, hope useful for everyone)
- 2014-01-08 18:26:40下载
- 积分:1
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chap12
《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)
- 2007-07-01 16:33:31下载
- 积分:1
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gamefive
高精度小数除法器设计与实现。
在FPGA开发板上实现小数除法器,输入输出信号N_in [15:0], D_in[15:0],N_in[15:0]小于D_in,即被除数小于除数,输出商Q_out[15:0]中Q[15]一定为0,Q[14:0]为商的小数部分。输入和计算结果通过VGA显示。(Precision fractional divider design and implementation. In the FPGA development board fractional divider, input and output signals N_in [15: 0], D_in [15: 0], N_in [15: 0] less than D_in, ie the dividend is less than the divisor, quotient output Q_out [15: 0] in Q [15] necessarily 0, Q [14: 0] for the business of the fractional part. Input and calculation results display by VGA.)
- 2017-01-01 17:32:25下载
- 积分:1