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Some_classic_examples_of_VHDL_language_source_code
VHDL语言的一些经典实例源代码,包括状态机,时序电路,组合逻辑电路等(Some classic examples of VHDL language source code, including the state machine, sequential circuits, combinational logic circuits)
- 2010-07-11 12:50:06下载
- 积分:1
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ug835-vivado-tcl-commands
说明: Vivado是Xilinx最新的FPGA设计工具,支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比,Vivado可以说是全新设计的。无论从界面、设置、算法,还是从对使用者思路的要求,都是全新的。看在Vivado上,Tcl已经成为唯一支持的脚本,此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s in the 7 series and beyond. Compared with the previous ISE design suite, Vivado can be said that the new design. No matter from the interface, settings, algorithms, or from the user ideas, are new. Look at Vivado, Tcl has become the only supported script, this file is vivado tcl command collection.)
- 2020-10-26 22:50:00下载
- 积分:1
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xilinx_usb_drivers_win10_x64
说明: win10的xilinx usb驱动,较新版本(Xilinx USB driver for win10, newer version)
- 2021-03-11 17:09:26下载
- 积分:1
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QPSK
用VHDL语言实现QPSK调制功能和解调功能,(Using VHDL language features QPSK modulation and demodulation functions,)
- 2021-04-26 15:28:46下载
- 积分:1
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(7,4)汉明码
汉明码学习,以(7,4)为例,仿真正常。(Hamming code learning, taking (7, 4) as an example, the simulation is normal.)
- 2021-03-29 17:19:10下载
- 积分:1
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SD卡控制器verilog
sd卡读写,仿真模型,testbanch测试文件(sdcard read write and sdcard model)
- 2021-04-21 16:28:49下载
- 积分:1
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AD
说明: 基于fpga的ad采样程序 可控制ad9226对信号进行采样(Ad9226 signal sampling can be controlled by ad9226 sampling program based on FPGA)
- 2020-12-19 17:09:10下载
- 积分:1
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GPS/BD开源原代码,verilog 有很强的借鉴意义
verilog编写的GPS /BD基带逻辑代码,包含跟踪相关部分代码,有比较好的借鉴意义。
- 2022-03-11 22:42:41下载
- 积分:1
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FPGA COMS传感器接口 LCD 移动终端源代码
用FPGA实现COMS传感器接入,LCD控制,及与ARM通信的源代码,包含matlab仿真及硬件原理图和手册,非常全面
- 2022-12-10 20:50:03下载
- 积分:1
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NiosII_mycpu
基于NiosII 的SOC FPGA验证系统,适用初学者学习Altra Quartus II软件,以及C语言 veriog,以及MCU调试流程
- 2022-03-19 06:31:20下载
- 积分:1