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ADS1115
本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型,16位,为IIC通信方式,调试较复杂,在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)
- 2013-08-23 22:49:26下载
- 积分:1
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fpga_coder_module
本人编写的FPGA光电编码器输入模块,没有实验,但仿真基本实现,希望有参考价值.(FPGA optical encoder input module, there is no experimental, but simulation technology, hope to have reference value.)
- 2021-04-21 01:58:50下载
- 积分:1
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s29gl256s
说明: s29gl256s nor flash 源代码(s29gl256s device source code)
- 2019-03-03 11:46:03下载
- 积分:1
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R_I_CPU
学校实验,用Verilog实现的单周期CPU,分别实现I型、R型、指令,使用的工具为ISE(School experiments, using Verilog to achieve a single cycle CPU, respectively, to achieve I type, R type, instruction, the use of tools for ISE)
- 2018-06-11 16:38:10下载
- 积分:1
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shuzishizhong
基于DE2-115开发板设计的一个数字钟,能进行正常的小时、分、秒计时功能,并分别由开发板上面的数码管显示秒(60s)、分(60min)、小时(24hours)的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)
- 2020-11-01 11:39:54下载
- 积分:1
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Verilog-SRAM
用verilog hdl语言编写的fpga与片外sram 的读写控制(With the verilog hdl language fpga sram chip with read and write control)
- 2020-12-09 15:39:18下载
- 积分:1
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Single_cpu
单周期CPU自己课程大作业做的,亲测好用,verilog语言,适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
- 2017-12-29 20:15:48下载
- 积分:1
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vga_ctl_640x480
VGA 640x480 driver in verilog
- 2010-08-16 02:48:43下载
- 积分:1
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xilinx_usb_drivers_win10_x64
win10的xilinx usb驱动,较新版本(Xilinx USB driver for win10, newer version)
- 2021-03-11 17:09:26下载
- 积分:1
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CircuitDesignwithVHDL[1]
这主要是学习vhdl和fpga设计的一些资料(study for vhdl and fpga)
- 2009-05-13 09:31:26下载
- 积分:1