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firhalfband
利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图，回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)
- 2020-07-03 21:40:02下载
- 积分：1
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shuzishizhong
基于DE2-115开发板设计的一个数字钟，能进行正常的小时、分、秒计时功能，并分别由开发板上面的数码管显示秒（60s）、分（60min）、小时（24hours）的时间。并具有手动调整时间的功能(DE2-115 board design based on a digital clock, and enables the normal hours, minutes, seconds chronograph function, and were above the development board digital display seconds (60s), points (60min), hours (24hours) time . And has a function to manually adjust the time)
- 2020-11-01 11:39:54下载
- 积分：1
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ps2_interface
封装PS2接口驱动，用verilog编写！适用于键盘，鼠标等PS2接口的器件。(failed to translate)
- 2013-05-05 10:48:42下载
- 积分：1
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viterbi
维特比译码，卷积编码，verilog编写，2,1,2编码(Victor than decoding, convolution code, verilog write, 2,1,2 coding
)
- 2011-12-08 23:10:45下载
- 积分：1
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3input_xor
用Hspice实现一个三输入异或门，并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)
- 2018-06-12 11:06:45下载
- 积分：1
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spi_slave
说明： xilinx 平台的SPI从接口实现源码，供参考学习(used xilinx,slave-spi interface.)
- 2019-04-21 12:08:29下载
- 积分：1
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tcp_ip_core_w_dhcp_latest.tar
以太网协议 TCP/IP/DHCP协议verilog实现(Ethernet IP/TCP/DHCP verilog source code)
- 2018-08-23 14:35:01下载
- 积分：1
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polyPhaseFilter
说明： 数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)
- 2019-12-24 09:58:51下载
- 积分：1
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risc_spm 处理单元
处理单元的 risc_spm 你可以求出其存储的程序对某些容易操作。
- 2023-03-09 16:40:03下载
- 积分：1
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pld_Tetris
基于FPGA cyclone III EP3C16F484C6的俄罗斯方块游戏。实现双人进行，屏幕倒置，分数显示，vga接口，键盘接口等功能(Tetris game based on FPGA cyclone III EP3C16F484C6 with functions including double players, screen upside down, score, vga and keyboard interface.)
- 2020-11-06 12:39:49下载
- 积分：1
