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digital-PLL
收集的关于数字锁相环的理论模型和分析讨论,适用于FPGA的数字电路设计。(Theoretical models and analysis and discussion about digital PLL collected for FPGA-based digital circuit design.)
- 2015-02-11 10:39:31下载
- 积分:1
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8051Core的源代码,Verilog编写,包括ALU、存储器、SP、dptr等诸多模块,十分完整。
8051Core的源代码,Verilog编写,包括ALU、存储器、SP、dptr等诸多模块,十分完整,已在Quartus上编译通过,确认无误。
- 2023-08-08 08:00:03下载
- 积分:1
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RapidIO_avalonst
RapidIO:使用Avalon-ST直通接口的实现方法,可以在fpga上实现(rapidio altera)
- 2017-05-31 22:50:11下载
- 积分:1
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CLZ_32bit
前导零的计算 (Calculation of leading zeros)
- 2021-03-31 21:29:09下载
- 积分:1
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基于FPGA的信号发生器20140506
说明: 基于FPGA的芯片信号发生器,利用Verilog语言实现信号发生器的各个模块单元,
实现的要求:正弦波、三角波、方波等;(Based on FPGA chip signal generator, using Verilog language to realize each module unit of the signal generator, Requirements: sine wave, triangle wave, square wave, etc;)
- 2019-12-30 11:48:26下载
- 积分:1
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Vivado基础实验
通过用vivado完成一个流水灯项目手把手教你如何使用vivado,内容十分详细。(Using vivado to complete a running light project, you can learn how to use vivado by hand. The content is very detailed.)
- 2018-12-06 16:14:45下载
- 积分:1
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squareLoop
利用平方环法提取同步载波的FPGA实现的仿真(FPGA implementation of synchronous carrier extraction using square loop method)
- 2021-01-11 17:18:49下载
- 积分:1
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UART_RX_
fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)
- 2020-06-18 04:00:01下载
- 积分:1
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新建 Microsoft Word 文档
八位串行乘法器
缺点:乘法功能是正确的,但计算一次乘法需要8个周期,因此可以看出串行乘法器速度比较慢、时延大。
优点:该乘法器所占用的资源是所有类型乘法器中最少的,在低速的信号处理中有广泛的使用。(Eight bit serial multiplierDisadvantages: the multiplication function is correct, but the computation of one multiplication requires 8 cycles, so it can be seen that the serial multiplier is slow and time-consuming.
Advantages: the multiplier occupies the smallest number of resources in all types of multipliers, and is widely used in low speed signal processing.)
- 2018-06-10 21:19:29下载
- 积分:1
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I2C_ise9migration
说明: IIC 的Verilog实现,工程是在Xilinx的ISE9.1上实现的(IIC of the Verilog implementation project was implemented on Xilinx' s ISE9.1)
- 2010-04-02 09:26:54下载
- 积分:1