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exp8
浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)
- 2020-09-26 12:07:46下载
- 积分：1
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示波器设计源工程
说明： 示波器设计，首先，AD模块对模拟信号进行采样，触发电路根据采样信号判断触发条件。满足触发条件后，连续采样一定数量的点（本系统中为640个点），存储到RAM中。峰峰值、频率计算模块对RAM中储存的波形数据进行计算，得到波形的频率以及峰峰值；VGA模块将波形显示出来，并显示计算得到的峰峰值和频率数值。(Firstly, the ad module samples the analog signal, and the trigger circuit judges the trigger condition according to the sampling signal. After meeting the trigger conditions, a certain number of points (640 points in this system) are sampled continuously and stored in RAM. The peak to peak and frequency calculation module calculates the waveform data stored in RAM to obtain the frequency and peak to peak of the waveform; the VGA module displays the waveform and displays the calculated peak to peak and frequency values.)
- 2021-01-02 17:29:54下载
- 积分：1
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multiplier_interface
verilog 写的工程，是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)
- 2012-09-21 10:04:54下载
- 积分：1
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UART Verilog sorce 代码和仿真代码和 FIFO 代码
它由 verilog 语言编程和主要代码是 UART，主要来源代码是 uart_receiver.v /uart_transmitter.v/lpm_mux0.v/myfifo.v......一些波形文件可以帮助您了解更多的模拟信息。
- 2022-03-24 03:32:08下载
- 积分：1
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util_gmii_to_rgmii
说明： rgmii代码编写，实现rgmii接口功能，可进行参考设计(The rgmii code is written to realize the function of rgmii interface, which can be used for reference design)
- 2021-03-18 10:19:20下载
- 积分：1
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abi123
encoding and decoding of audio signal
- 2013-02-02 18:59:16下载
- 积分：1
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Lab1_flash_led
说明： EGO_1流水灯显示代码步骤过程全都有适合初学者练手(EGO_1 nxoiaocijpwjcpoewopvkpowevko)
- 2020-12-22 11:39:08下载
- 积分：1
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lab4showTAs
4 seg display, button debouncer, and controller for parking meter
- 2010-11-10 16:17:42下载
- 积分：1
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sd模型
完整的Verilog验证模型，包括设备完整的状态。(Complete verilog Verification Model)
- 2020-06-16 09:00:01下载
- 积分：1
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crc16_8bit.v
FPGA用于实现crc16编码的verlog源程序，用到的请下载。(FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.)
- 2012-11-08 13:45:14下载
- 积分：1
