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flashZ
FPGA控制m25p16flash芯片读写控制spi协议
可实现擦除写入读出功能(SPI protocol for read and write control of m25p16 flash chip controlled by FPGA
Erase Write-Read Function)
- 2018-12-19 16:10:59下载
- 积分：1
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cn60
六十进制计数器用于计数等操作，代码的实现方式很简单(Six decimal counter for counting operation, the code is very simple implementations)
- 2014-12-10 10:10:50下载
- 积分：1
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视频解码之RGB转YUV模块(Verilog)
资源描述
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
视频解码之RGB转YUV模块(Verilog)
- 2022-02-25 21:46:18下载
- 积分：1
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new
1、PC和寄存器组使用时钟触发。
2、指令存储器和数据存储器存储单元宽度一律使用8位，即一个字节的存储单位。
3、控制器部分可以考虑用控制信号真值表方法（有共性部分）与用case语句方法逐个产生各指令其它控制信号相配合，注意：信号必须与状态配合。。当然，还可以用其它方法，自己考虑。
4、试用的汇编程序，而且必须包含所要求的所有指令。Slt、sltu指令必须检查两种情况：“小于”和“大于等于”；beq、bne指令必须检查两种情况：“等”和“不等”。这段汇编程序必须尽量优化，同时，给出每条指令在内存中的地址。(1, PC and register groups are clocked.
2, the command memory and data memory storage unit width will use 8 bits, that is, a byte storage unit.
3, the controller part can be considered with the control signal truth table method (common part) and with the case statement method to produce each command other control signal match, Note: the signal must be with the state. The Of course, you can also use other methods to consider their own.
4, try the assembler, and must contain all the required instructions. Slt, sltu instruction must check two cases: "less than" and "greater than or equal to"; beq, bne instruction must check two cases: "wait" and "unequal". This assembler must be optimized as much as possible, giving the address of each instruction in memory.)
- 2017-10-19 09:44:13下载
- 积分：1
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55593397xapp592
GTH 和SMPTE IP 实现 SDI视频接收(SDI Video Receiving Based on GTH and SMPTE IP)
- 2019-02-18 16:09:33下载
- 积分：1
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fpalign_struct
floating point alignment
- 2013-03-11 16:53:31下载
- 积分：1
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seven_lcd
七段数码管显示的时钟程序VHDL代码 ISE编译环境(SEVEN seg VHDL ISE CLOCK)
- 2009-12-08 11:09:15下载
- 积分：1
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facman
一款在Verilog实现的吃豆人游戏，采用VGA接口，在Nexys3开发板上运行无误。(A pac-man game implemented via Verilog, using VGA interface, perfectly run on Nexys 3)
- 2021-03-31 07:39:09下载
- 积分：1
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pll
用FPGA实现数字锁相环，开发环境为ISE(Using FPGA digital phase-locked loop, development environment for ISE)
- 2021-03-19 18:29:19下载
- 积分：1
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FPGA双口RAM的Verilog代码实现
本程序是本人按照教程一步一步生成的，内部有textbench可以进行仿真验证。
- 2022-03-20 22:15:54下载
- 积分：1
