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32bit_add_exercise
32位全加器，另有一个采用流水线的版本，是基于verilog语言的，很实用，希望对大家有所帮助(32-bit full adder, while a pipelined version，code is based on verilog language, it is practical, we hope to help)
- 2016-07-19 14:31:17下载
- 积分：1
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galois
example of BCH and RS codecs
- 2009-06-10 11:26:17下载
- 积分：1
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A VEILOG HDL procedures, can be applied directly,
一个VEILOG HDL程序，可以直接应用，-A VEILOG HDL procedures, can be applied directly,
- 2023-02-01 17:30:03下载
- 积分：1
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BT656_RGB
说明： 将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)
- 2021-03-22 09:29:17下载
- 积分：1
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一个同步有限状态机（FSM）的设计是一个数字的共同任务…
Designing a synchronous finite state machine (FSM) is a common task for a digital
logic engineer. This paper discusses a variety of issues regarding FSM design using
Synopsys Design Compiler. Verilog and VHDL coding styles are presented, and
different methodologies are compared using real-world examples.
- 2022-01-26 02:12:10下载
- 积分：1
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exercise
使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)
- 2014-02-20 16:20:33下载
- 积分：1
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rtl_DRAM
本程式為使用Verilog語言寫控制DRAM的控制模塊, 可以簡易的控制DRAM IC, 本程式已經過系統驗證.(program for the use of the Verilog language to write the control of DRAM control module, be easy to control DRAM IC, the program has been systematically verified.)
- 2006-12-05 11:31:42下载
- 积分：1
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Ver_I2C_eeprom
用verilog编写的I2C——E2PROM模型。适用于各种型号的E2PROM，代码内部有参数可选。(Written in verilog I2C- E2PROM model. E2PROM, the internal code applicable to various types of optional parameters.)
- 2013-04-10 16:14:03下载
- 积分：1
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HDLC接口协议的FPGA实现使用verilog
HDLC接口协议的FPGA实现使用verilog-design of HDLC
- 2022-06-02 20:47:21下载
- 积分：1
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Using VHDL language description of the memory read and write, user
用vhdl语言描写的存储器的读写，通俗易懂，简单实用。-Using VHDL language description of the memory read and write, user-friendly, simple and practical.
- 2022-05-27 15:20:00下载
- 积分：1
