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modelsim_example_c
modelsim仿真，大量vhdl程序，验证，很有价值！(The ModelSim Simulation, a large number of VHDL procedures, validation, great value!)
- 2013-05-05 15:11:06下载
- 积分：1
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并行通信代码（调试通过）
并口通讯代码
并口通讯代码（调试通过）
--该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers
- 2022-05-20 22:29:56下载
- 积分：1
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16-bit-CPU
单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书(Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions)
- 2020-08-02 10:28:35下载
- 积分：1
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myfir
verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件(order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file)
- 2020-10-05 16:47:44下载
- 积分：1
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100个VHDL的例子
100个VHDL的例子-100 examples of VHDL
- 2022-06-15 19:10:07下载
- 积分：1
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ex11
说明： 该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)
- 2020-09-09 11:58:09下载
- 积分：1
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Project_Gbit
说明： pc与fpga之间通过千兆以太网交换机实现网络通信(Network communication between PC and FPGA via Gigabit Ethernet switch)
- 2020-06-17 20:40:04下载
- 积分：1
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shuzishizhong
这是基于verilog hdl的数字时钟源代码，能够实现时分秒的计时，可以手动进行调时与调分。(This is based on the digital clock verilog hdl source code, can be achieved when every minute of the time, you can adjust the time manually adjusting points.)
- 2013-12-10 22:21:55下载
- 积分：1
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cic_dec_8_five
CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频(CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion)
- 2010-03-02 12:53:31下载
- 积分：1
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BmpDecoder
适用于Altera FPGA Nios II平台uClinux OpenCV之BmpDecoder的源码(Souce code of BmpDecoder for Altera FPGA Nios II uClinux OpenCV)
- 2011-02-11 16:43:45下载
- 积分：1
