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主要是RS
主要是RS-232串行接口技术并且通过了串行收发器UART的开发实例演示了接口设计的基本步骤程序-Is RS-232 serial interface technology and, through a serial UART transceiver development of interface design examples demonstrate the basic steps of the procedure
- 2022-03-17 15:36:56下载
- 积分：1
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VGA_yanse
用fpga实现VGA16色真彩的图片显示,且在AX301实验板上已经调试过(VGA16 achieve true color with fpga pictures show, and in the AX301 has been tuned breadboard)
- 2021-02-05 17:59:57下载
- 积分：1
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用verilog hdl 硬件描述语言写的一个范例程序，led的，扩展性极强，欢迎大家下载使用。...
用verilog hdl 硬件描述语言写的一个范例程序，led的，扩展性极强，欢迎大家下载使用。-Verilog hdl using hardware description language to write an example of the procedure, led, and highly scalable, welcome to download.
- 2022-03-06 09:45:48下载
- 积分：1
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Clutter-Filtering-
。给出了时域滤波的基本原理以及通常采用的
IIR 椭圆地物杂波滤波器的设计方法。重点研究了回归滤波器这一时域滤波算
法。从正交多项式的拟合出发，给出了回归滤波器抑制地物杂波的基本原理及
其滤波实现过程。通过对回归滤波器的计算复杂度的研究，寻找使回归滤波器
计算量最小的正交多项式。分析了回归滤波器频率响应特性，比较了回归滤波
器与IIR 椭圆地物杂波滤波器的计算复杂度。利用仿真的雷达信号，分析了回
归滤波器的地物杂波抑制性能。回归滤波器实际上是一高通滤波器，它在滤掉
低频地物杂波的同时，对落在滤波器阻带内的天气回波信号同样会造成衰减。
在天气回波信号谱宽固定的情况下，通过改变天气回波信号的平均多普勒频率，
分析了回归滤波器对它的衰减情况。在基于一组实际采集的雷达信号的基础上，
给出了回归滤波器的地物杂波抑制比随着滤波器阶数的变化情况。(Firstly, this dissertation introduces the research background and significance of
ground clutter suppression, analyzes the characteristics of the ground clutter and
weather signals in the Doppler weather radars and simulates Doppler radar echo
signals (It includes ground clutter, weather echo signals and the mixture of them).
The simulated signals are used later to study the time and frequency domain ground
clutter suppression.
Secondly, this dissertation talks about the time domain filtering, gives the basic
theory of time domain filtering and describes the design method of the usually used
fifth-order elliptic infinite impulse response (IIR) ground clutter filter. In the time
domain, the work focuses on the regression filter. From the orthogonal polynomials
fit, this dissertation gives the basic theory of the regression filter for ground clutter
suppression and the filtering process using a regression filter. Through the study of
the computational complexity of regression)
- 2012-07-09 22:12:11下载
- 积分：1
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pwm
实现pwm波的输出，按键可调占空比的，可通过连接pwm输出值led灯以检测占空比的变化(To realize the output of the PWM wave, key adjustable duty ratio, but through the connection PWM output value led lamp with testing duty ratio changes
)
- 2020-12-20 21:19:08下载
- 积分：1
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uart
说明： 串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分：1
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Hoang_ha_PIC18_for_proteus.2
library of protues aaaaaaaa
- 2013-11-12 12:00:40下载
- 积分：1
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ffirr_166i
fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。
(fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)
- 2012-06-10 17:54:50下载
- 积分：1
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File name: ADC0809.vhd features: Based on the VHDL language, easy to control imp...
文件名：ADC0809.vhd功能：基于VHDL语言，实现对ADC0809简单控制说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟号，这里由FPGA的系统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。-File name: ADC0809.vhd features: Based on the VHDL language, easy to control implementation of the ADC0809 Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock number, here by the FPGA system clock (50MHz) frequency by 256 points to be clk1 (195KHz ) as the conversion ADC0809 clock job.
- 2023-07-04 18:20:03下载
- 积分：1
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shift_regeister
用blockram实现移位寄存器，开发语言为verilog hdl(Shift register with blockram achieve the development language for the verilog hdl)
- 2020-08-13 22:18:29下载
- 积分：1
