登录
首页 » VHDL » 数字钟的实现 FPGA上运行 VHDL编写

数字钟的实现 FPGA上运行 VHDL编写

于 2023-08-20 发布 文件大小:16.35 MB
0 22
下载积分: 2 下载次数: 1

代码说明:

数字钟的实现 FPGA上运行 VHDL编写-Digital clock running on the FPGA to achieve the preparation of VHDL

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • Camera-Interface-Overview
    主要讲述了数码相机MIPI接口协议说明,工作模式及信号传输原理等(Camera Interface Overview)
    2014-01-20 22:19:32下载
    积分:1
  • arccos
    一个求反余弦的cordic算法,整个工程。包括仿真。可以直接打开。(An inverse cosine of the cordic seeking algorithms, the whole project. Including the simulation. Can be directly opened.)
    2009-11-04 22:48:00下载
    积分:1
  • 50 cases of practical CPLD design, very classic CPLD design, including 50 typica...
    CPLD实用设计50例,非常经典的CPLD设计,包含50个实际的典型应用,涉及直流电机PWM驱动,编码等内容,有了这50例,举一反三,就会了很多应用-50 cases of practical CPLD design, very classic CPLD design, including 50 typical practical applications, involving PWM DC motor driver, coding, etc., with these 50 cases, giving top priority will be a lot of applications
    2022-02-25 20:47:07下载
    积分:1
  • aes
    Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.
    2009-12-20 14:16:40下载
    积分:1
  • electric-8.08
    The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including: * Custom IC layout * Schematic Capture (digital and analog) * Textual Languages such as VHDL and Verilog (The ElectricTM VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:* Custom IC layout* Schematic Capture (digital and analog)* Textual Languages such as VHDL and Verilog)
    2009-01-09 20:01:17下载
    积分:1
  • VHDL 0~
    程序用VHDL实现: 利用一秒定时测量频率 并且显示,范围0~-VHDL 0~
    2022-05-15 03:55:50下载
    积分:1
  • LDPC码的消息节点(Bitnode)消息更新过程的VHDL语言实现
    LDPC码的消息节点(Bitnode)消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
    2022-12-16 00:40:03下载
    积分:1
  • 用VHDL和verilog实现的四人抢答器
    用VHDL和verilog实现的四人抢答器-using VHDL and verilog realization of four Responder
    2023-07-17 00:15:04下载
    积分:1
  • 这个是用verilog语言编写的基于FPGA的交通灯控制器,分别控制四个方向上的交通灯的通断...
    这个是用verilog语言编写的基于FPGA的交通灯控制器,分别控制四个方向上的交通灯的通断-The verilog language is FPGA-based traffic light controller, respectively, the four direction control of traffic lights-off
    2022-03-22 05:17:26下载
    积分:1
  • 8位乘法器的VHDL代码
    资源描述该乘法器可用于过滤器,算术运算和;
    2022-08-14 19:11:01下载
    积分:1
  • 696522资源总数
  • 104042会员总数
  • 18今日下载