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verilogCRC32
32位bit输入的CRC32校验,verilog的代码,以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)
- 2012-03-07 10:22:58下载
- 积分:1
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suzimiaobiao
数字秒表的实现,我还写个具体的过程要求等,(there is function of clock,it very useful)
- 2011-09-20 14:28:30下载
- 积分:1
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i2c_master_ip_for_nios
i2c master ip for altera nios, add in qsys
- 2018-03-02 14:50:44下载
- 积分:1
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EncoderUsingif
encoder using else if statement
- 2015-05-21 13:41:00下载
- 积分:1
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Fractional_Time_Delay
Used for Time shifting discrete signals, it can do both integral and fractional sampling period delay. Original.
- 2020-12-16 22:29:12下载
- 积分:1
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ethernet-verilog
非常详细的千兆以太网MAC verilog代码,可以供硬件设计时有关网络的开发参考(Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference)
- 2020-09-19 11:27:57下载
- 积分:1
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Tuart_tx_rxh
该工程用verilog编写,已通过串口调试助手调试通过,接收模块采采用8倍波特率采样数据,有较好的滤波功能,在PC上完成自发自收功能。
(The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC spontaneous self-closing function.)
- 2012-08-26 10:39:49下载
- 积分:1
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20753
基于VHDL的FPGA开发快速入门·技巧·实例 ,电子工程师创新设计必备宝典系列之FPGA开发全攻,未来,FPGA 开
发能力对工程师而言将成为类似C 语言的基础能力之一,面对这样的发展趋势,你还能简单地将FPGA 当成一种逻辑器件吗?还能对FPGA 的发展无动于衷吗?(基于VHDL的FPGA开发快速入门·技巧·实例 )
- 2013-12-19 09:33:31下载
- 积分:1
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the program two integers and the sum of squared output
本程序实现两个整数平方和相加并且输出结果-the program two integers and the sum of squared output
- 2023-08-09 04:10:02下载
- 积分:1
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pci144_vhdl
PCI vhdl for Fpga designer to design PCI IP
- 2007-12-23 20:58:15下载
- 积分:1