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pipeline_FPGA
FPGA流水线设计的资料,可以作为学习FPGA开发并行操作的一个经典教材,具有很好的指导作用。(FPGA pipeline design information can be developed as a learning FPGA parallel operation of a classic textbook, has a good guide.)
- 2011-07-02 12:00:57下载
- 积分:1
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MIPS_LANG
说明: verilog实现misp架构,并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)
- 2020-06-18 04:40:02下载
- 积分:1
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具有多种功能的电子钟:闹钟、定时和修改…
具有多种功能的电子钟:闹钟,报时和修改,定时闹钟,报时时间,带闹钟,报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
- 2022-03-12 23:49:24下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1
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RAM控制的VHDL实现 真的很有用
RAM控制的VHDL实现 真的很有用 -VHDL implementation of the RAM control true true useful useful
- 2023-09-01 03:40:03下载
- 积分:1
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word_aligner_8bit_test
说明: CMV2000的对齐模块,适用于其他对齐模块,自行修改(CMV2000 alignment module, suitable for other alignment modules, self-modifying)
- 2020-06-16 07:00:01下载
- 积分:1
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dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
- 2022-11-12 18:25:03下载
- 积分:1
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VHDL写的PWM发生器,仿真通过,波形基本完美,可以用于直流电机的控制...
VHDL写的PWM发生器,仿真通过,波形基本完美,可以用于直流电机的控制-PWM generator written in VHDL, simulation is passed, the basic waveform perfect, can be used for DC motor control
- 2022-09-19 14:15:03下载
- 积分:1
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可配置CRC参考设计 xilinx提供的VHDL
可配置CRC参考设计 xilinx提供的VHDL-configurable CRC reference design for Xilinx VHDL
- 2022-01-23 10:27:39下载
- 积分:1
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ALTERA NIOS处理器,用VHDL在QUARTUS下编写,用NIOS SHELL调试通过,实验LCD液晶显示...
ALTERA NIOS处理器,用VHDL在QUARTUS下编写,用NIOS SHELL调试通过,实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
- 2022-03-20 10:53:06下载
- 积分:1