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raised-cosine-filter
代码实现了一个根升余弦成型滤波器,2PAM信号通过此成型滤波器,并且匹配接收,画出了发送和接收波形,验证了代码的正确性。(The code designs a root raised cosine filter,2PAM signal transmitted through the filter and matched using the same filter, I plot the transmitted signal and received signal to verify the correctness of the code.)
- 2012-11-09 21:59:53下载
- 积分:1
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liuy
一个精确时钟的v-log程序,只用一个全局时钟,增加了精确度(An accurate clock in the v-log program, only one global clock, increased accuracy)
- 2010-08-25 12:26:25下载
- 积分:1
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SRAM
进阶实验之SRAM测试,由verilog编写,可直接对sram进行存写(Advanced SRAM test experiments, written by the verilog, can be stored directly on the sram write)
- 2011-08-18 01:58:56下载
- 积分:1
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1
verilog 典型电路设计包含各种常用电路的源码和详细的解释,适合新手使用(Verilog typical circuit design includes a variety of commonly used circuit source code and detailed explanations, suitable for beginners to use
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- 2014-03-19 10:48:41下载
- 积分:1
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uaf42
使用uaf42设计的有源滤波器,高通滤波器的设计参数记录(Using uaf42 design active filters, high-pass filter design parameters recorded)
- 2012-09-09 21:49:49下载
- 积分:1
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7位数码管的显示
实现7位数码管的显示,可以优先解决用户很多问题,不懂得可以问我,不用客气,7位数码管的显示很简单的
- 2023-06-09 10:50:03下载
- 积分:1
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divider
用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)
- 2020-11-19 11:39:37下载
- 积分:1
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Door opener
模块规格:门通过滑动打开。每侧都有一个红外线传感器和一个光电管。如果有人靠近门,传感器会向芯片发送信息。电动机将可由传感器切换的门向两个方向移动。如果门受到障碍物的阻碍,则电动机的电流会升高。在这种情况下,系统会收到反馈,如果门完全打开或关闭,则结束该过程。如果这个标志在门关上的时候出现(有人或有什么东西被门包围了),它会迫使门完全打开。过了一会儿门又想关上。系统也可以手动切换(打开或关闭)。
- 2022-08-14 21:05:23下载
- 积分:1
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DA_TLC5620
是基于FPGA的5620的数模转换芯片底层的应用程序,希望有用。(Is a digital-analog converter chip underlying the 5620 FPGA-based applications, and I hope useful.)
- 2013-12-15 10:43:21下载
- 积分:1
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cordic
说明: 实现可连续输入数据做三角函数变换处理,通过verilog代码实现,(It realizes triangular function transformation for continuous input data.)
- 2020-06-21 22:40:01下载
- 积分:1