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The_Ten_Commands_of_Excellent_Design
介绍了FPGA设计的十大准则，对初学者很有用，对于工作多年的同志，也会有整理总结的好处(Describes the FPGA design of the top ten criteria are useful for beginners, for many years comrades, there will be finishing the benefits of the summary)
- 2009-09-26 16:44:29下载
- 积分：1
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vgachar
VGA显示程序VHDL版本，适用于ALTERA的CPLD(VGA display program applies ALTERA CPLD)
- 2012-05-31 10:35:14下载
- 积分：1
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udp_send1
基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data_valid,
input gtx_clk,
output logic tx_en(UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows:
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data)
- 2016-03-10 15:23:29下载
- 积分：1
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jitter_eliminate
verilog描述的实用消抖电路，采用三个D触发器和一个JK触发器。使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏(verilog description of the practical elimination shake circuit, using three D flip-flop and a JK flip-flop. Prepared source files using the emacs , iverilog simulation adopted, within the simulation images png screenshots)
- 2009-11-24 15:51:44下载
- 积分：1
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Micron_SDRAM_DDR2Simulation_model_Verilog
DDR2 SDRAM仿真模型，适合于ModelSim下工作，请先阅读readme(DDR2 SDRAM Simulation Model which is suitable for modelsim. Please read readme file firstly.)
- 2020-10-29 17:49:57下载
- 积分：1
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FPGAmotor
FPGA在直流电机调速中的应用,利用fpga进行PID闭环控制(tell us speed control for DC motor by FPGA,use fpga for PID circle control)
- 2010-11-03 20:40:42下载
- 积分：1
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AHB
// 4 entry deep fast fifo
module fifo4(clk, rst, clr, din, we, dout, re, full, empty);
parameter dw = 8;
input clk, rst;
input clr;
input [dw:1] din;
input we;
output [dw:1] dout;
input re;
output full, empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [dw:1] mem[0:3];
reg [1:0] wp;
reg [1:0] rp;
wire [1:0] wp_p1;
wire [1:0] wp_p2;
wire [1:0] rp_p1;
wire full, empty;
reg gb;
///////////////////////////////////
- 2022-01-25 20:06:27下载
- 积分：1
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bldc_motor_control_design_example
无刷直流电机 VHDL VERILOG 控制,速度环，RS232 串口接收发送 始终分频 PWM生成 电机相序 actel FPGA使用-VERILOG BLDC control of the use of actel FPGA( actel VERILOG BLDC control of the use of actel FPGA)
- 2020-10-29 09:19:57下载
- 积分：1
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SOUND_PLAY6
WM8731芯片的音效处理verilog代码，
WM8731芯片是音频ADCDAC芯片(WM8731 audio processing chip verilog code, WM8731 chip audio ADC DAC chip)
- 2013-12-14 14:12:10下载
- 积分：1
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multi_booth
说明： 基于quartus的布斯乘法器的verilog 实现。布斯乘法算法是计算机中一种利用数的2的补码形式来计算乘法的算法。该算法由安德鲁·唐纳德·布斯于1950 年发明，当时他在伦敦大学伯克贝克学院做晶体学研究。布斯曾使用过台式计算器，由于用这种计算器来做移位计算比加法快，他发明了该算法来加快计算速度。(The verilog codes of booth multiplier based on quartus. Booth multiplication algorithm is a computer algorithm using the complement form of number 2 to calculate the multiplication. The algorithm was invented in 1950 by Andrew Donald booth, who was working on crystallography at birkbeck college, university of London. Booth used a desktop calculator, and because it was faster to do shifts than to add, he invented the algorithm to speed up the calculations.)
- 2019-01-06 10:03:08下载
- 积分：1
