dma_hussam
代码说明:
verilog code for dma
文件列表:
25.3.10\access_tasks.v
25.3.10\dma.v
25.3.10\dma_tb.v
25.3.10\DPRAM512x32.v
25.3.10\fifo.v
25.3.10\interrupt.v
25.3.10\main_dma.v
25.3.10\parameters.v
25.3.10\registers.v
25.3.10\reset_and_error_tasks.v
25.3.10\tests.v
25.3.10\dma_tb.cr.mti
25.3.10\work\_info
25.3.10\work\_temp\vlogs93rzj
25.3.10\work\_temp\vlogtw6xj9
25.3.10\work\_temp\vlogjwf9aa
25.3.10\work\_temp\vlog8m80rd
25.3.10\work\_vmake
25.3.10\work\dma\_primary.vhd
25.3.10\work\dma\verilog.psm
25.3.10\work\dma\verilog.prw
25.3.10\work\dma\_primary.dbs
25.3.10\work\dma\_primary.dat
25.3.10\work\dma_tb\_primary.vhd
25.3.10\work\dma_tb\verilog.psm
25.3.10\work\dma_tb\verilog.prw
25.3.10\work\dma_tb\_primary.dbs
25.3.10\work\dma_tb\_primary.dat
25.3.10\work\@d@p@r@a@m512x32\_primary.vhd
25.3.10\work\@d@p@r@a@m512x32\verilog.psm
25.3.10\work\@d@p@r@a@m512x32\verilog.prw
25.3.10\work\@d@p@r@a@m512x32\_primary.dbs
25.3.10\work\@d@p@r@a@m512x32\_primary.dat
25.3.10\work\fifo\_primary.vhd
25.3.10\work\fifo\verilog.psm
25.3.10\work\fifo\verilog.prw
25.3.10\work\fifo\_primary.dbs
25.3.10\work\fifo\_primary.dat
25.3.10\work\interrupt\_primary.vhd
25.3.10\work\interrupt\verilog.psm
25.3.10\work\interrupt\verilog.prw
25.3.10\work\interrupt\_primary.dbs
25.3.10\work\interrupt\_primary.dat
25.3.10\work\addr_gen\_primary.vhd
25.3.10\work\addr_gen\verilog.psm
25.3.10\work\addr_gen\verilog.prw
25.3.10\work\addr_gen\_primary.dbs
25.3.10\work\addr_gen\_primary.dat
25.3.10\work\mem_cntrl_fsm\_primary.vhd
25.3.10\work\mem_cntrl_fsm\verilog.psm
25.3.10\work\mem_cntrl_fsm\verilog.prw
25.3.10\work\mem_cntrl_fsm\_primary.dbs
25.3.10\work\mem_cntrl_fsm\_primary.dat
25.3.10\work\main_dma\_primary.vhd
25.3.10\work\main_dma\verilog.psm
25.3.10\work\main_dma\verilog.prw
25.3.10\work\main_dma\_primary.dbs
25.3.10\work\main_dma\_primary.dat
25.3.10\work\registers\_primary.vhd
25.3.10\work\registers\verilog.psm
25.3.10\work\registers\verilog.prw
25.3.10\work\registers\_primary.dbs
25.3.10\work\registers\_primary.dat
25.3.10\dma_Tests_Report.dat
25.3.10\registers.v.bak
25.3.10\vsim.wlf
25.3.10\tests.v.bak
25.3.10\dma_tb.v.bak
25.3.10\dmat_tb.cr.mti
25.3.10\work\_temp
25.3.10\work\dma
25.3.10\work\dma_tb
25.3.10\work\@d@p@r@a@m512x32
25.3.10\work\fifo
25.3.10\work\interrupt
25.3.10\work\addr_gen
25.3.10\work\mem_cntrl_fsm
25.3.10\work\main_dma
25.3.10\work\registers
25.3.10\work
25.3.10
DMA FDR.ppt
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