4bit-adder_verilog

代码说明：

  4位全加法器的modelsim工程带testbench(Four full-adder modelsim project with testbench)

文件列表：

4位加法器—verilog
..................\adder4.cr.mti,513,2007-08-18
..................\adder4.mpf,16770,2007-08-18
..................\adder4.v,375,2007-08-18
..................\adder4_testbench.v,937,2007-08-03
..................\chart

..................\htm" target=_blank>transcript,4703,2007-08-18
..................\vsim.wlf,32768,2007-08-18
..................\wave


..................\work
..................\....\adder4
..................\....\......\verilog.asm,5275,2007-08-18
..................\....\......\_primary.dat,379,2007-08-18
..................\....\......\_primary.vhd,403,2007-08-18
..................\....\adder4_testbench
..................\....\................\verilog.asm,8995,2007-08-18
..................\....\................\_primary.dat,722,2007-08-18
..................\....\................\_primary.vhd,92,2007-08-18
..................\....\htm" target=_blank>_info,384,2007-08-18