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SANUPS_PMC_J
附件为小日本的50KW逆变器的方案，太阳能控制架构图，希望对大家有用。附件为小日本的50KW逆变器的方案，太阳能控制架构图，希望对大家有用。(Attached is a small Japanese 50KW inverter solutions, solar control chart, we want to be useful. Attached is a small Japanese 50KW inverter solutions, solar control chart, we want to be useful.)
- 2013-12-11 16:30:48下载
- 积分：1
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1602-digital-clock
基于C51单片机的1602液晶屏显示时间，实现计时功能(Based on 1602 C51 LCD shows time, realize the timing function)
- 2015-09-01 21:12:52下载
- 积分：1
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BoardDemo
自己写的C51开发板上硬件驱动，可作为工程开发模板，芯片是stc12c5060s2 上传项目是数字语音存储与回放(C51 development board hardware drivers to write their own, as the engineering development of a template, the chip is stc12c5060s2 upload project digital voice storage and playback)
- 2013-03-09 00:35:12下载
- 积分：1
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ZStack-CC2530-2.5.1a-BMP180
基于zigbee技术CC2530 开发采集大气压(Development and Collection of Atmospheric Pressure Based on Zigbee Technology CC2530)
- 2020-06-22 22:00:01下载
- 积分：1
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JN-AN-1229
说明： zigbee document upload 23/7/2019
- 2020-06-21 18:00:02下载
- 积分：1
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51chuankoutiaoshi
51单片机串口调试程序一列,希望对大家有用(51 Single-chip serial debugging a program, in the hope that useful to everybody)
- 2008-05-20 12:10:22下载
- 积分：1
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NRF24L01
NRF24L01Information Program(NRF24L01 Information Program)
- 2014-03-17 15:32:58下载
- 积分：1
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cc1120-1200-1101
本源码程序为射频通信驱动代码，采用IAR system软件开发，以MSP430单片机为主控芯片，程序集成了CC1120，CC1200，CC1101等多种射频芯片，在使用时可通过用户自己屏蔽不需要的芯片，程序中均已文件分好，各种芯片的代码互不干扰。我已经通过测试，改程序可以直接运行，但用户在使用时需进行IAR软件的路径配置(The source program for RF communication driver code, using the IAR system software development, MSP430 single chip as the main control chip, the program integrates CC1120, CC1200, CC1101 and other radio frequency chip, by the users themselves do not shield chip when in use, the program have the good, various chip code do not interfere with each other. I have passed the test, reform program can be run directly, but the path to configure user required when using IAR software
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- 2020-09-19 09:27:53下载
- 积分：1
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ADC_DualModeInterleaved
stm32f4 adc 的代码，双通道，用DMA保存数据。(stm32f4 family c code, adc
This example provides a short description of how to use the ADC peripheral to
convert a regular channel in Dual interleaved mode using DMA in mode 3 with 5Msps.
DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions.
The Dual interleaved delay is configured 6 ADC clk cycles.
On each DMA request (two data items are available) two bytes representing two
ADC-converted data items are transferred as a half word.
The data transfer order is similar to that of the DMA mode 2.
A DMA request is generated each time 2 data items are available
1st request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
2nd request: ADC_CDR[15:0] = (ADC2_DR[7:0] << 8) | ADC1_DR[7:0]
The ADC1 and ADC2 are configured to convert ADC Channel 12, with conversion
triggered by software.
By this way, ADC channel 12 is converted each 6 cycles.
In this example, the system clock is 168MHz, APB2 =84MHz and ADC clock = APB2 /2.
Since ADCCLK=)
- 2013-10-14 19:06:26下载
- 积分：1
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21__ISSN_1392-1215_Control-of-Asymmetrical-Multil
Control of Asymmetrical Multilevel Inverter Using Artificial Neural Network
- 2013-10-07 03:16:32下载
- 积分：1
