RANGEN

代码说明：

  2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)

文件列表：

RANGEN
......\clock_div.bsf,2193,2013-08-20
......\DOC
......\...\设计方案说明.docx,0,2013-08-18
......\RANGEN.asm.rpt,7206,2013-08-21
......\RANGEN.bsf,1993,2013-08-20
......\RANGEN.done,26,2013-08-21
......\RANGEN.fit.rpt,519540,2013-08-21
......\RANGEN.fit.smsg,314,2013-08-21
......\RANGEN.fit.summary,618,2013-08-21
......\RANGEN.flow.rpt,11713,2013-08-21
......\RANGEN.jdi,4074,2013-08-21
......\RANGEN.map.rpt,79036,2013-08-21
......\RANGEN.map.summary,476,2013-08-21
......\RANGEN.pin,33010,2013-08-21
......\RANGEN.qpf,1273,2013-08-19
......\RANGEN.qsf,6779,2013-08-21
......\RANGEN.sof,496595,2013-08-21
......\RANGEN.sta.rpt,803408,2013-08-21
......\RANGEN.sta.summary,1641,2013-08-21
......\RANGEN_stp.stp,267246,2013-08-20
......\RTL
......\...\clock_div.v,4404,2013-08-21
......\...\clock_div.v.bak,4140,2013-08-20
......\...\RANGEN.v,2634,2013-08-21
......\...\RANGEN.v.bak,2123,2013-08-19
......\...\sigxnor.v,1549,2013-08-21
......\...\sigxnor.v.bak,1635,2013-08-21
......\...\synclk_buf.v,1476,2013-08-21
......\...\synclk_buf.v.bak,560,2013-08-20
......\sigxnor.bsf,1972,2013-08-21
......\synclk_buf.bsf,1799,2013-08-20
......\top_Block.bdf,6569,2013-08-21