-
AI
说明： this is a tic-tac-toe game.... no one can win...try it.. :)
- 2009-07-11 15:18:28下载
- 积分：1
-
EULER1
说明： Euler 回路问题
.问题描述：
对于给定的图G 和G 中的2 个顶点v 和w，连接顶点v 和w 且经过图中每条边恰好1 次
的路径称为顶点v 和w 之间的1 条Euler 路。当v=w 时得到一条首尾相接的Euler 回路。
.编程任务：
对于给定的图G，编程计算图G 的一条Euler 回路。
.数据输入：
由文件input.txt 给出输入数据。第1 行有2 个正整数n 和m，表示给定的图G 有n 个
顶点和m 条边，顶点编号为1，2，…，n。接下来的m 行中，每行有2 个正整数u,v ，表示
图G 的一条边(u,v) 。
.结果输出:
将编程计算出的Euler 回路输出到文件output.txt 。如果不存在Euler 回路，则输出-1。(Euler circuit problem. Problem description : for a given graph G and G of two vertices v, w, connectivity and vertex v w map through which each side precisely the path to a meeting called vertices v, w between a Euler Road. When v = w be an end-to-end circuit Euler. . Programming tasks : for a given graph G, programming terms of a graph G Euler circuit. . Data input : from the document input.txt given input data. Line 1 has two positive integers n and m, to the graph G with n vertices and m edges and vertices numbered 1, 2, ..., n. Next m OK, every trip has two positive integer u, v, said of a graph G edge (u, v). . Results output : Programming will be calculated by Euler circuit output to a file output.txt. If there is no Euler circuit, the output 1.)
- 2006-03-29 21:31:15下载
- 积分：1
-
DesignPatterns-of-Summary
java深入浅出设计模式的 一个总结 (Head First Design Patterns of Summary)
- 2012-12-17 12:12:52下载
- 积分：1
-
KMSpico.v10.2.0
KMSpico V10 keygen license for microsoft office and windows
- 2019-02-12 14:51:45下载
- 积分：1
-
IOCP(I/O Completion Port)Winsock例子
IOCP(I/O Completion Port)Winsock例子-IOCP(I/O Completion Port)Winsock example
- 2022-02-21 01:52:01下载
- 积分：1
-
SA
说明： 层状面波模拟退火反演，用于简单的层状地层面波的反演，设置好初始模型，添加实测的频散曲线进行反演对比(Simulated annealing inversion of layered surface wave)
- 2018-04-16 20:27:30下载
- 积分：1
-
sourcefiles
window下使用j2ee的jms工具做的网络应用的一个架构程序(window using the jms Providing the tools to do a network application framework procedures)
- 2005-06-29 19:04:25下载
- 积分：1
-
good
好的
- 2022-06-02 05:13:58下载
- 积分：1
-
LogicSynthesis2_CMOSBasics
LogicSynthesis2_CMOSBasics
Key Problem: Timing assumption
during prelayout synthesis widely
differs from the post layout reality.
• This happens because the
interconnect delay dominates the
overall propagation delay in DSM
(Deep Sub‐Micron) technologies.
• As a result getting a timing closure
becomes a challenge
- 2014-07-07 17:51:39下载
- 积分：1
-
C
说明： C程序设计(谭浩强)，对初学C语言的同志们很有帮助。(c language)
- 2012-08-14 16:06:22下载
- 积分：1
