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digital-design-and-synthesis

于 2012-10-23 发布 文件大小:11889KB
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  Verilog HDL 数字设计与综合,夏宇闻译。本书重点关注如何应用verilog语言进行数字电路和系统的设计和验证,不仅讲解语法,更从基本概念讲起,逐渐过渡到编程语言接口以及逻辑综合等高级主题。(The design and synthesis of Verilog HDL digital, Xia Wen translation. The book focused on how to apply the verilog language for the design and verification of digital circuits and systems, not only explain the grammar, the more I start from the basic concept, and a gradual transition to advanced topics such as programming language interface and logic synthesis.)

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