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blif2verilog-v1.2

于 2013-11-30 发布文件大小:69KB

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代码说明：

将BLIF（Berkeley Logic Interchange Format）格式的电路转换为verilog代码，使用perl编写，需要perl环境才能使用。内含BLIF格式的官方说明。(Translate BLIF（Berkeley Logic Interchange Format）circuit to verilog description, the translator need perl environment to run. Please check you have related tools. Also include a offical document about BLIF explanation.)

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blif2verilog-v1.2

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