CLZ32

代码说明：

  针对32位MIPS微处理器中CLZ指令（对单个字高位连零进行计数）的实现电路，使用了类似于超前进位的逻辑结构。包含测试文档，以及Design Compile所用的环境和脚本。(The CLZ instruction counts the number of leading zeros in a word. The 32-bit word in the GPR rs is scanned from most-significant to least-significant bit.The number of leading zeros is counted and the result is written to the GPR rd. If all 32 bits are cleared in the GPR rs, the result written to the GPR rd is 32. )

文件列表：

CLZ
...\.synopsys_dc.setup,248,2013-12-13
...\CLZ.cr.mti,975,2013-12-13
...\CLZ.mpf,69978,2013-12-13
...\CLZ16.v,1275,2013-12-13
...\CLZ32.v,510,2013-12-13
...\CLZ_testbench.v,1264,2013-12-13
...\constrain.tcl,184,2013-12-13
...\run.tcl,863,2013-12-13
...\htm" target=_blank>transcript,1882,2013-12-13
...\vsim.wlf,32768,2013-12-13
...\work
...\....\@c@l@z16
...\....\........\verilog.asm,8272,2013-12-13
...\....\........\verilog.rw,3381,2013-12-13
...\....\........\_primary.dat,1831,2013-12-13
...\....\........\_primary.dbs,4019,2013-12-13
...\....\........\_primary.vhd,211,2013-12-13
...\....\@c@l@z32
...\....\........\verilog.asm,4680,2013-12-13
...\....\........\verilog.rw,1915,2013-12-13
...\....\........\_primary.dat,738,2013-12-13
...\....\........\_primary.dbs,1435,2013-12-13
...\....\........\_primary.vhd,211,2013-12-13
...\....\@c@l@z_testbench
...\....\................\verilog.asm,9232,2013-12-13
...\....\................\verilog.rw,1043,2013-12-13
...\....\................\_primary.dat,1605,2013-12-13
...\....\................\_primary.dbs,1483,2013-12-13
...\....\................\_primary.vhd,86,2013-12-13
...\....\htm" target=_blank>_info,1145,2013-12-13
...\....\_temp
...\....\_vmake,26,2013-12-13