sync-and-asyn_FIFO_verilog

代码说明：

  同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

文件列表：

001-FIFO经验谈-含有实例分析.pdf,1071122,2013-05-20
001-FPGA学习小结(FIFO)-陈建军.pdf,127771,2013-05-20
001-Simulation_and_Synthesis_Techniques_for_Asynchronous_FIFO_Design.pdf,551376,2013-05-22
001-Simulation_and_Synthesis_Techniques_for_Async_FIFO_Design_with_Asynchronous_Pointer_Comparisons.pdf,212057,2013-05-21
asynchronous_fifo1.v,2431,2013-05-22
asynchronous_fifo1_tb.v,2261,2013-05-22
async_fifo_beha.v,2921,2013-05-22
async_fifo_beha_tb.v,2245,2013-05-22
rptr_empty.v,1698,2013-05-22
rptr_empty_tb.v,1325,2013-05-21
sync_r2w.v,918,2013-05-22
sync_r2w_tb.v,1115,2013-05-21
sync_w2r.v,927,2013-05-22
sync_w2r_tb.v,1174,2013-05-21
wptr_full.v,1799,2013-05-22
wptr_full_tb.v,1240,2013-05-21
同步与异步FIFO的verilog实现-2013-05-22.docx,849443,2013-05-22