dpll

代码说明：

  用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )

文件列表：

dpll
....\div_8.v,399,2013-09-14
....\even_f.v,310,2013-09-22
....\IDcounter.v,2777,2013-09-14
....\IDcounter_t.v,1612,2013-10-02
....\jk_ff.v,139,2013-09-21
....\kcounter.v,4123,2013-09-22
....\property.sv,311,2013-10-21
....\tb_dac.v,758,2013-10-02
....\tb_IDcounter.v,1193,2013-10-02
....\tb_jk.v,344,2013-09-21
....\tb_k.v,745,2013-09-18
....\tb_top.v,900,2013-10-03
....\test_top.sv,944,2013-10-21
....\top.v,611,2013-09-21