frequency-agility
于 2015-10-15 发布
文件大小:2412KB
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代码说明：
本程序为捷变频信号的verilog源代码设计实现的仿真，并含有相应捷变频信号在MATLAB仿真的结果(The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB)
文件列表：
捷变频
......\skip.m,414,2015-01-05
......\捷变频.rar,2605699,2015-10-15
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