AD7865test1

代码说明：

  verilog hdl写的利用fpga控制ad7865进行多路ad数据采集的程序源代码。(err)

文件列表：

AD7865test1
...........\AD7865test
...........\..........\AD7865.bsf
...........\..........\AD7865.v
...........\..........\AD7865test.asm.rpt
...........\..........\AD7865test.bdf
...........\..........\AD7865test.cdf
...........\..........\AD7865test.done
...........\..........\AD7865test.eda.rpt
...........\..........\AD7865test.fit.eqn
...........\..........\AD7865test.fit.rpt
...........\..........\AD7865test.fit.summary
...........\..........\AD7865test.flow.rpt
...........\..........\AD7865test.map
...........\..........\AD7865test.map.eqn
...........\..........\AD7865test.map.rpt
...........\..........\AD7865test.map.summary
...........\..........\AD7865test.pin
...........\..........\AD7865test.pof
...........\..........\AD7865test.qpf
...........\..........\AD7865test.qsf
...........\..........\AD7865test.qws
...........\..........\AD7865test.rar
...........\..........\AD7865test.sof
...........\..........\AD7865test.tan.rpt
...........\..........\AD7865test.tan.summary
...........\..........\AD7865test_assignment_defaults.qdf
...........\..........\AD7865test_bak.bdf
...........\..........\cnt_500.bsf
...........\..........\cnt_500.v
...........\..........\db
...........\..........\..\AD7865test.db_info
...........\..........\..\AD7865test.eco.cdb
...........\..........\..\AD7865test.sld_design_entry.sci
...........\..........\..\altsyncram_1kb2.tdf
...........\..........\..\altsyncram_7kb2.tdf
...........\..........\..\altsyncram_9kb2.tdf
...........\..........\..\altsyncram_jjb2.tdf
...........\..........\..\altsyncram_ljb2.tdf
...........\..........\..\altsyncram_tjb2.tdf
...........\..........\..\altsyncram_ujb2.tdf
...........\..........\..\altsyncram_vjb2.tdf
...........\..........\..\cmpr_fnh.tdf
...........\..........\..\cmpr_gnh.tdf
...........\..........\..\cntr_0dc.tdf
...........\..........\..\cntr_0id.tdf
...........\..........\..\cntr_0ja.tdf
...........\..........\..\cntr_1ja.tdf
...........\..........\..\cntr_4ja.tdf
...........\..........\..\cntr_8id.tdf
...........\..........\..\cntr_mbb.tdf
...........\..........\..\cntr_pia.tdf
...........\..........\..\cntr_qia.tdf
...........\..........\..\cntr_tia.tdf
...........\..........\..\cntr_ubb.tdf
...........\..........\..\cntr_ulb.tdf
...........\..........\..\cntr_vcc.tdf
...........\..........\..\cntr_via.tdf
...........\..........\..\cntr_vlb.tdf
...........\..........\..\decode_9ie.tdf
...........\..........\pin.txt
...........\..........\pll.bsf
...........\..........\pll.v
...........\..........\pll_bb.v

...........\..........\pll_waveforms.html
...........\..........\simulation
...........\..........\..........\modelsim
...........\..........\..........\........\AD7865test.vo
...........\..........\..........\........\AD7865test_modelsim.xrf
...........\..........\..........\........\AD7865test_v.sdo
...........\..........\sopc_builder_debug_log.txt
...........\..........\stp1.stp
...........\..........\stp1_auto_signaltap_0.txt
...........\..........\talkback
...........\..........\........\AD7865test.asm.talkback.xml
...........\..........\........\AD7865test.eda.talkback.xml
...........\..........\........\AD7865test.fit.talkback.xml
...........\..........\........\AD7865test.map.talkback.xml
...........\..........\........\AD7865test.tan.talkback.xml