ddr3_sun

代码说明：

  使用DDR3IP核进行仿真，写入读取数据(Using DDR3IP core to simulate, write and read data)

文件列表：

ddr3_sun\ddr3.gise, 30108 , 2018-12-31
ddr3_sun\ddr3.xise, 47331 , 2018-12-31
ddr3_sun\ddr3_model_isim_beh.exe, 94720 , 2018-12-31
ddr3_sun\ddr3_tb.fdo, 5454 , 2018-12-25
ddr3_sun\ddr3_tb.udo, 380 , 2018-08-29
ddr3_sun\ddr3_tb.v, 32493 , 2018-09-01
ddr3_sun\ddr3_tb1.fdo, 5459 , 2018-12-30
ddr3_sun\ddr3_tb1.udo, 381 , 2018-08-31
ddr3_sun\ddr3_tb1.v, 35010 , 2018-12-31
ddr3_sun\ddr3_tb1_beh.prj, 4649 , 2018-12-31
ddr3_sun\ddr3_tb1_isim_beh.exe, 94720 , 2018-12-31
ddr3_sun\ddr3_tb1_isim_beh.wdb, 7041713 , 2018-12-31
ddr3_sun\ddr3_tb1_wave.fdo, 426 , 2018-08-31
ddr3_sun\ddr3_tb3.v, 948 , 2018-09-01
ddr3_sun\ddr3_tb_wave.fdo, 425 , 2018-08-29
ddr3_sun\example_top.fdo, 6889 , 2018-08-30
ddr3_sun\example_top.udo, 384 , 2018-08-30
ddr3_sun\example_top1.wlf, 507904 , 2018-08-31
ddr3_sun\example_top_wave.fdo, 429 , 2018-08-30
ddr3_sun\fuse.log, 28543 , 2018-12-31
ddr3_sun\fuse.xmsgs, 5563 , 2018-12-31
ddr3_sun\fuseRelaunch.cmd, 238 , 2018-12-31
ddr3_sun\ipcore_dir\coregen.cgp, 239 , 2018-08-29
ddr3_sun\ipcore_dir\coregen.log, 258 , 2018-08-30
ddr3_sun\ipcore_dir\create_a.tcl, 1254 , 2018-08-30
ddr3_sun\ipcore_dir\create_DDR3.tcl, 1257 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\datasheet.txt, 2705 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\DDR3.csv, 5561 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\docs\phy_only_support_readme.txt, 608 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\docs\ug586_7Series_MIS.pdf, 79723 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\log.txt, 4872 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\create_ise.bat, 3137 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_icon_cg.xco, 1413 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_ila_basic_cg.xco, 3898 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_ila_rdpath_cg.xco, 3900 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_ila_wrpath_cg.xco, 3899 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_vio_async_in_sync_out_cg.xco, 1619 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_vio_sync_async_out72_cg.xco, 1616 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\example_top.cpj, 757534 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\example_top.ucf, 29839 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\example_top.xdc, 40093 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\ise_flow.bat, 4602 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\makeproj.bat, 3137 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\readme.txt, 4232 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\rem_files.bat, 12849 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\rem_files.tcl, 8287 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\set_ise_prop.tcl, 5296 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\par\xst_options.txt, 194 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\example_top.v, 35866 , 2018-09-02
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_afifo.v, 6196 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_cmd_gen.v, 35000 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_cmd_prbs_gen.v, 10591 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_data_prbs_gen.v, 4725 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_init_mem_pattern_ctr.v, 39110 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_memc_flow_vcontrol.v, 15690 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_memc_traffic_gen.v, 32751 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_rd_data_gen.v, 12293 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_read_data_path.v, 28068 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_read_posted_fifo.v, 7842 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_s7ven_data_gen.v, 38798 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_tg_prbs_gen.v, 11144 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_tg_status.v, 4748 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_traffic_gen_top.v, 29333 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_vio_init_pattern_bram.v, 13203 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_write_data_path.v, 7212 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\rtl\traffic_gen\mig_7series_v1_9_wr_data_gen.v, 13187 , 2013-10-14
ddr3_sun\ipcore_dir\DDR3\example_design\sim\ddr3_model.v, 152505 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\ddr3_model_parameters.vh, 235718 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\isim_files.prj, 8406 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\isim_options.tcl, 3232 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\isim_run.bat, 3300 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\readme.txt, 7435 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\sim.do, 6041 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\sim_tb_top.v, 36410 , 2018-09-02
ddr3_sun\ipcore_dir\DDR3\example_design\sim\wiredly.v, 5456 , 2018-08-31
ddr3_sun\ipcore_dir\DDR3\example_design\sim\xsim_files.prj, 8398 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\xsim_options.tcl, 3193 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\sim\xsim_run.bat, 3325 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\synth\example_top.lso, 6 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\synth\example_top.prj, 4951 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\example_design\synth\synplify_pro.tcl, 6105 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\mig.prj, 4423 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\constraints\DDR3.ucf, 29828 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\constraints\DDR3.xdc, 40072 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\log.txt, 8294 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\clocking\mig_7series_v1_9_clk_ibuf.v, 4796 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\clocking\mig_7series_v1_9_infrastructure.v, 24158 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\clocking\mig_7series_v1_9_iodelay_ctrl.v, 9718 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\clocking\mig_7series_v1_9_tempmon.v, 15167 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_arb_mux.v, 19702 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_arb_row_col.v, 18940 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_arb_select.v, 26779 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_bank_cntrl.v, 25941 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_bank_common.v, 18372 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_bank_compare.v, 10847 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_bank_mach.v, 31504 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_bank_queue.v, 23288 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_bank_state.v, 36754 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_col_mach.v, 16676 , 2018-08-29
ddr3_sun\ipcore_dir\DDR3\user_design\rtl\controller\mig_7series_v1_9_mc.v, 42050 , 2018-08-29