uart_fifo

代码说明：

  一份带有FIFO缓存的UART源码，采用verilog编写，实现批量数据的传输，数据缓存量可以通过修改源码中的FIFO的深度来改变。(This is a UART with FIFO. The UART is programmed using verilog, it can transmit or receive batch data. The amount of data buffered can be changed by changing the depth of FIFO.)

文件列表：

uart_fifo
.........\fifo.v,677,2015-04-21
.........\UART.v,570,2015-04-20
.........\UART_RX.v,2193,2015-04-20
.........\UART_TX.v,2148,2015-04-20