Altera-FPGA_CPLD-design-Advanced

代码说明：

  《Altera FPGA_CPLD设计 高级篇》详细介绍FPGA应用于高级特性，LogicLock设计，时序约束，设计优化，高级工具及系统级设计技术，是深入学习FPGA的重要材料(" Altera FPGA_CPLD advanced part design" details FPGA used in advanced features, LogicLock design, timing constraints, design optimization, system-level design tools and advanced technology, in-depth study is an important material for FPGA)

文件列表：

Altera FPGA_CPLD设计 高级篇
...........................\Altera FPGA_CPLD设计 高级篇.pdf,24211701,2008-01-26