ddr3control

代码说明：

  8位突发长度，一次64bit数据读写，MIG核(DDR3 controll implimention)

文件列表：

ddr3control\c0_ddr3_model_parameters.vh
ddr3control\c1_ddr3_model_parameters.vh
ddr3control\ddr3control.gise
ddr3control\ddr3control.xise
ddr3control\iseconfig\ddr3control.projectmgr
ddr3control\iseconfig\mig_39_2.xreport
ddr3control\mig_39_2\docs\ds186.pdf
ddr3control\mig_39_2\docs\ug406.pdf
ddr3control\mig_39_2\docs\ug406d.pdf
ddr3control\mig_39_2\example_design\datasheet.txt
ddr3control\mig_39_2\example_design\log.txt
ddr3control\mig_39_2\example_design\mig.prj
ddr3control\mig_39_2\example_design\par\bitgen_options.ut
ddr3control\mig_39_2\example_design\par\constraints.xcf
ddr3control\mig_39_2\example_design\par\create_ise.bat
ddr3control\mig_39_2\example_design\par\example_top.cdc
ddr3control\mig_39_2\example_design\par\example_top.ucf
ddr3control\mig_39_2\example_design\par\icon5_cg.xco
ddr3control\mig_39_2\example_design\par\ila384_8_cg.xco
ddr3control\mig_39_2\example_design\par\ise_flow.bat
ddr3control\mig_39_2\example_design\par\makeproj.bat
ddr3control\mig_39_2\example_design\par\readme.txt
ddr3control\mig_39_2\example_design\par\rem_files.bat
ddr3control\mig_39_2\example_design\par\set_ise_prop.tcl
ddr3control\mig_39_2\example_design\par\vio_async_in256_cg.xco
ddr3control\mig_39_2\example_design\par\vio_sync_out32_cg.xco
ddr3control\mig_39_2\example_design\par\xst_options.txt
ddr3control\mig_39_2\example_design\rtl\controller\arb_mux.v
ddr3control\mig_39_2\example_design\rtl\controller\arb_row_col.v
ddr3control\mig_39_2\example_design\rtl\controller\arb_select.v
ddr3control\mig_39_2\example_design\rtl\controller\bank_cntrl.v
ddr3control\mig_39_2\example_design\rtl\controller\bank_common.v
ddr3control\mig_39_2\example_design\rtl\controller\bank_compare.v
ddr3control\mig_39_2\example_design\rtl\controller\bank_mach.v
ddr3control\mig_39_2\example_design\rtl\controller\bank_queue.v
ddr3control\mig_39_2\example_design\rtl\controller\bank_state.v
ddr3control\mig_39_2\example_design\rtl\controller\col_mach.v
ddr3control\mig_39_2\example_design\rtl\controller\mc.v
ddr3control\mig_39_2\example_design\rtl\controller\rank_cntrl.v
ddr3control\mig_39_2\example_design\rtl\controller\rank_common.v
ddr3control\mig_39_2\example_design\rtl\controller\rank_mach.v
ddr3control\mig_39_2\example_design\rtl\controller\round_robin_arb.v
ddr3control\mig_39_2\example_design\rtl\ecc\ecc_buf.v
ddr3control\mig_39_2\example_design\rtl\ecc\ecc_dec_fix.v
ddr3control\mig_39_2\example_design\rtl\ecc\ecc_gen.v
ddr3control\mig_39_2\example_design\rtl\ecc\ecc_merge_enc.v
ddr3control\mig_39_2\example_design\rtl\ip_top\c0_memc_ui_top.v
ddr3control\mig_39_2\example_design\rtl\ip_top\c1_memc_ui_top.v
ddr3control\mig_39_2\example_design\rtl\ip_top\clk_ibuf.v
ddr3control\mig_39_2\example_design\rtl\ip_top\ddr2_ddr3_chipscope.v
ddr3control\mig_39_2\example_design\rtl\ip_top\example_top.v
ddr3control\mig_39_2\example_design\rtl\ip_top\infrastructure.v
ddr3control\mig_39_2\example_design\rtl\ip_top\iodelay_ctrl.v
ddr3control\mig_39_2\example_design\rtl\ip_top\memc_ui_top.v
ddr3control\mig_39_2\example_design\rtl\ip_top\mem_intfc.v
ddr3control\mig_39_2\example_design\rtl\phy\circ_buffer.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_ck_iob.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_clock_io.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_control_io.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_data_io.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_dly_ctrl.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_dm_iob.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_dqs_iob.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_dq_iob.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_init.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_pd.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_pd_top.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_rdclk_gen.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_rdctrl_sync.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_rddata_sync.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_rdlvl.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_read.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_top.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_write.v
ddr3control\mig_39_2\example_design\rtl\phy\phy_wrlvl.v
ddr3control\mig_39_2\example_design\rtl\phy\rd_bitslip.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\afifo.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\cmd_gen.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\cmd_prbs_gen.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\data_prbs_gen.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\init_mem_pattern_ctr.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\mcb_flow_control.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\mcb_traffic_gen.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\rd_data_gen.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\read_data_path.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\read_posted_fifo.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\sp6_data_gen.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\tg_status.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\v6_data_gen.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\write_data_path.v
ddr3control\mig_39_2\example_design\rtl\traffic_gen\wr_data_gen.v
ddr3control\mig_39_2\example_design\rtl\ui\ui_cmd.v
ddr3control\mig_39_2\example_design\rtl\ui\ui_rd_data.v
ddr3control\mig_39_2\example_design\rtl\ui\ui_top.v
ddr3control\mig_39_2\example_design\rtl\ui\ui_wr_data.v
ddr3control\mig_39_2\example_design\sim\c0_ddr3_model.v
ddr3control\mig_39_2\example_design\sim\c0_ddr3_model_parameters.vh
ddr3control\mig_39_2\example_design\sim\c1_ddr3_model.v
ddr3control\mig_39_2\example_design\sim\c1_ddr3_model_parameters.vh
ddr3control\mig_39_2\example_design\sim\ddr3_model.v