8b10bEncoderDecoder-SourceCode (1)

代码说明：

  lattice的官方8b10b代码, 1012年版本，diamond3.5编译。(lattice 8b10b encoder decoder code)

文件列表：

RD1012_rev01.2\docs, 0 , 2011-03-31
RD1012_rev01.2\docs\rd1012.pdf, 304521 , 2011-03-31
RD1012_rev01.2\docs\rd1012_readme.txt, 18415 , 2011-04-05
RD1012_rev01.2\project, 0 , 2011-03-25
RD1012_rev01.2\project\4k, 0 , 2011-03-25
RD1012_rev01.2\project\4k\verilog, 0 , 2011-03-25
RD1012_rev01.2\project\4k\verilog\8b_10b_enc_dec.lct, 1749 , 2010-06-24
RD1012_rev01.2\project\4k\vhdl, 0 , 2011-03-25
RD1012_rev01.2\project\4k\vhdl\8b_10b_enc_dec.lct, 1813 , 2010-06-24
RD1012_rev01.2\project\ecp_ec, 0 , 2011-03-25
RD1012_rev01.2\project\ecp_ec\verilog, 0 , 2011-03-25
RD1012_rev01.2\project\ecp_ec\verilog\8b_10b_enc_dec.lpf, 96 , 2011-01-31
RD1012_rev01.2\project\ecp_ec\vhdl, 0 , 2011-03-25
RD1012_rev01.2\project\ecp_ec\vhdl\8b_10b_enc_dec.lpf, 96 , 2010-06-23
RD1012_rev01.2\project\ecp2m, 0 , 2011-03-25
RD1012_rev01.2\project\ecp2m\verilog, 0 , 2011-03-25
RD1012_rev01.2\project\ecp2m\verilog\enc_dec.lpf, 81 , 2011-01-31
RD1012_rev01.2\project\ecp2m\verilog\Strategy1.sty, 304 , 2011-01-31
RD1012_rev01.2\project\ecp2m\vhdl, 0 , 2011-03-25
RD1012_rev01.2\project\ecp2m\vhdl\enc_dec.lpf, 81 , 2011-01-31
RD1012_rev01.2\project\ecp2m\vhdl\Strategy1.sty, 133 , 2011-03-25
RD1012_rev01.2\project\ecp3, 0 , 2011-03-25
RD1012_rev01.2\project\ecp3\verilog, 0 , 2011-03-25
RD1012_rev01.2\project\ecp3\verilog\enc_dec.lpf, 81 , 2011-01-31
RD1012_rev01.2\project\ecp3\verilog\Strategy1.sty, 231 , 2011-02-25
RD1012_rev01.2\project\ecp3\vhdl, 0 , 2011-03-25
RD1012_rev01.2\project\ecp3\vhdl\enc_dec.lpf, 81 , 2011-03-29
RD1012_rev01.2\project\ecp3\vhdl\Strategy1.sty, 133 , 2011-03-24
RD1012_rev01.2\project\xo, 0 , 2011-03-25
RD1012_rev01.2\project\xo\verilog, 0 , 2011-03-25
RD1012_rev01.2\project\xo\verilog\8b_10b_enc_dec.lpf, 97 , 2010-06-21
RD1012_rev01.2\project\xo\vhdl, 0 , 2011-03-25
RD1012_rev01.2\project\xo\vhdl\8b_10b_enc_dec.lpf, 97 , 2010-06-22
RD1012_rev01.2\project\xo2, 0 , 2011-03-25
RD1012_rev01.2\project\xo2\verilog, 0 , 2011-03-25
RD1012_rev01.2\project\xo2\verilog\enc_dec.lpf, 81 , 2011-03-31
RD1012_rev01.2\project\xo2\verilog\Strategy1.sty, 625 , 2011-01-31
RD1012_rev01.2\project\xo2\vhdl, 0 , 2011-03-25
RD1012_rev01.2\project\xo2\vhdl\enc_dec.lpf, 79 , 2011-03-31
RD1012_rev01.2\project\xo2\vhdl\Strategy1.sty, 133 , 2011-03-25
RD1012_rev01.2\project\xp2, 0 , 2011-03-25
RD1012_rev01.2\project\xp2\verilog, 0 , 2011-03-25
RD1012_rev01.2\project\xp2\verilog\enc_dec.lpf, 96 , 2010-06-28
RD1012_rev01.2\project\xp2\verilog\Strategy1.sty, 133 , 2011-02-25
RD1012_rev01.2\project\xp2\vhdl, 0 , 2011-03-25
RD1012_rev01.2\project\xp2\vhdl\enc_dec.lpf, 96 , 2010-06-23
RD1012_rev01.2\project\xp2\vhdl\Strategy1.sty, 133 , 2011-03-24
RD1012_rev01.2\simulation, 0 , 2011-03-25
RD1012_rev01.2\simulation\4k, 0 , 2011-03-25
RD1012_rev01.2\simulation\4k\verilog, 0 , 2011-03-25
RD1012_rev01.2\simulation\4k\verilog\tb_top_net_8b10b_tfa.udo, 1510 , 2010-06-24
RD1012_rev01.2\simulation\4k\verilog\tb_top_net_8b10b_tffa.udo, 1973 , 2010-06-24
RD1012_rev01.2\simulation\4k\vhdl, 0 , 2011-03-25
RD1012_rev01.2\simulation\4k\vhdl\tb_top_net_8b10b_vhda.udo, 1429 , 2010-06-24
RD1012_rev01.2\simulation\4k\vhdl\tb_top_net_8b10b_vhdaf.udo, 1789 , 2010-06-24
RD1012_rev01.2\simulation\ecp_ec, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp_ec\verilog, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp_ec\verilog\tb_top_net_8b10b_tf.udo, 1510 , 2010-06-23
RD1012_rev01.2\simulation\ecp_ec\verilog\tb_top_net_8b10b_tff.udo, 1992 , 2010-06-23
RD1012_rev01.2\simulation\ecp_ec\vhdl, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp_ec\vhdl\tb_top_net_8b10b_vhd.udo, 1451 , 2010-06-22
RD1012_rev01.2\simulation\ecp_ec\vhdl\tb_top_net_8b10b_vhdf.udo, 2078 , 2010-06-23
RD1012_rev01.2\simulation\ecp2m, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp2m\verilog, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp2m\verilog\enc_dec_enc_dec_vo.sdf, 161804 , 2011-01-31
RD1012_rev01.2\simulation\ecp2m\verilog\enc_dec_enc_dec_vo.vo, 93535 , 2011-01-31
RD1012_rev01.2\simulation\ecp2m\verilog\rtlsim.do, 85 , 2011-03-25
RD1012_rev01.2\simulation\ecp2m\verilog\timesim.do, 188 , 2011-03-25
RD1012_rev01.2\simulation\ecp2m\vhdl, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp2m\vhdl\enc_dec_enc_dec_vho.sdf, 178772 , 2011-03-24
RD1012_rev01.2\simulation\ecp2m\vhdl\enc_dec_enc_dec_vho.vho, 223670 , 2011-03-24
RD1012_rev01.2\simulation\ecp2m\vhdl\rtlsim.do, 81 , 2011-04-05
RD1012_rev01.2\simulation\ecp2m\vhdl\timesim.do, 185 , 2011-04-05
RD1012_rev01.2\simulation\ecp3, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp3\verilog, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp3\verilog\enc_dec_enc_dec_vo.sdf, 161804 , 2011-01-31
RD1012_rev01.2\simulation\ecp3\verilog\enc_dec_enc_dec_vo.vo, 93535 , 2011-01-31
RD1012_rev01.2\simulation\ecp3\verilog\rtlsim.do, 84 , 2011-03-25
RD1012_rev01.2\simulation\ecp3\verilog\timesim.do, 187 , 2011-03-25
RD1012_rev01.2\simulation\ecp3\vhdl, 0 , 2011-03-25
RD1012_rev01.2\simulation\ecp3\vhdl\enc_dec_enc_dec_vho.sdf, 165254 , 2011-03-24
RD1012_rev01.2\simulation\ecp3\vhdl\enc_dec_enc_dec_vho.vho, 213183 , 2011-03-24
RD1012_rev01.2\simulation\ecp3\vhdl\rtlsim.do, 80 , 2011-04-05
RD1012_rev01.2\simulation\ecp3\vhdl\timesim.do, 184 , 2011-04-05
RD1012_rev01.2\simulation\xo, 0 , 2011-03-25
RD1012_rev01.2\simulation\xo\verilog, 0 , 2011-03-25
RD1012_rev01.2\simulation\xo\verilog\tb_top_net_8b10b_tf.udo, 1513 , 2010-06-21
RD1012_rev01.2\simulation\xo\verilog\tb_top_net_8b10b_tff.udo, 1995 , 2010-06-21
RD1012_rev01.2\simulation\xo\vhdl, 0 , 2011-03-25
RD1012_rev01.2\simulation\xo\vhdl\tb_top_net_8b10b_vhd.udo, 1451 , 2010-06-22
RD1012_rev01.2\simulation\xo\vhdl\tb_top_net_8b10b_vhdf.udo, 2081 , 2010-06-22
RD1012_rev01.2\simulation\xo2, 0 , 2011-03-25
RD1012_rev01.2\simulation\xo2\verilog, 0 , 2011-03-31
RD1012_rev01.2\simulation\xo2\verilog\enc_dec_enc_dec_vo.sdf, 164874 , 2011-03-31
RD1012_rev01.2\simulation\xo2\verilog\enc_dec_enc_dec_vo.vo, 180212 , 2011-03-31
RD1012_rev01.2\simulation\xo2\verilog\rtlsim.do, 87 , 2011-03-25
RD1012_rev01.2\simulation\xo2\verilog\timesim.do, 190 , 2011-03-25
RD1012_rev01.2\simulation\xo2\vhdl, 0 , 2011-03-25
RD1012_rev01.2\simulation\xo2\vhdl\enc_dec_enc_dec_vho.sdf, 173690 , 2011-03-25
RD1012_rev01.2\simulation\xo2\vhdl\enc_dec_enc_dec_vho.vho, 1046802 , 2011-03-25