MemoryGame-master

代码说明：

  在开发板EGO1上实现的图形记忆游戏，白块按下确认建，黑色块不按确认键(memory game in verilog)

文件列表：

MemoryGame-master
.................\project_4.cache
.................\...............\compile_simlib
.................\...............\..............\activehdl
.................\...............\..............\ies
.................\...............\..............\modelsim
.................\...............\..............\questa
.................\...............\..............\riviera
.................\...............\..............\vcs
.................\...............\wt
.................\...............\..\java_command_handlers.wdf,291,2017-04-10
.................\...............\..\project.wpc,62,2017-04-10
.................\...............\..\synthesis.wdf,3749,2017-04-06
.................\...............\..\synthesis_details.wdf,100,2017-04-06
.................\...............\..\webtalk_pa.xml,1486,2017-04-10
.................\...............\..\xsim.wdf,256,2017-03-30
.................\project_4.hw
.................\............\hw_1
.................\............\....\hw.xml,678,2017-04-10
.................\............\....\wave
.................\............\project_4.lpr,343,2017-04-04
.................\project_4.ip_user_files
.................\.......................\ipstatic
.................\.......................\README.txt,130,2017-03-30
.................\project_4.runs
.................\..............\impl_1
.................\..............\......\.init_design.begin.rst,181,2017-04-06
.................\..............\......\.init_design.end.rst,0,2017-04-06
.................\..............\......\.opt_design.begin.rst,181,2017-04-06
.................\..............\......\.opt_design.end.rst,0,2017-04-06
.................\..............\......\.place_design.begin.rst,181,2017-04-06
.................\..............\......\.place_design.end.rst,0,2017-04-06
.................\..............\......\.route_design.begin.rst,181,2017-04-06
.................\..............\......\.route_design.end.rst,0,2017-04-06
.................\..............\......\.vivado.begin.rst,179,2017-04-06
.................\..............\......\.vivado.end.rst,0,2017-04-06
.................\..............\......\.Vivado_Implementation.queue.rst,0,2017-04-06
.................\..............\......\.write_bitstream.begin.rst,181,2017-04-06
.................\..............\......\.write_bitstream.end.rst,0,2017-04-06
.................\..............\......\gen_run.xml,9265,2017-04-06
.................\..............\......\htr.txt,389,2017-04-06
.................\..............\......\init_design.pb,1886,2017-04-06
.................\..............\......\ISEWrap.js,7308,2017-04-06
.................\..............\......\ISEWrap.sh,1622,2017-04-06
.................\..............\......\opt_design.pb,5366,2017-04-06
.................\..............\......\place_design.pb,22485,2017-04-06
.................\..............\......\project.wdf,1953,2017-04-06
.................\..............\......\route_design.pb,10657,2017-04-06
.................\..............\......\rundef.js,1332,2017-04-06
.................\..............\......\runme.bat,229,2017-04-06
.................\..............\......\runme.log,24295,2017-04-06
.................\..............\......\runme.sh,1204,2017-04-06
.................\..............\......\top_module.bit,2192120,2017-04-06
.................\..............\......\top_module.tcl,4374,2017-04-06
.................\..............\......\top_module.vdi,24151,2017-04-06
.................\..............\......\top_module_4524.backup.vdi,21070,2017-03-30
.................\..............\......\top_module_6620.backup.vdi,20678,2017-03-31
.................\..............\......\top_module_clock_utilization_routed.rpt,14337,2017-04-06
.................\..............\......\top_module_control_sets_placed.rpt,5983,2017-04-06
.................\..............\......\top_module_drc_opted.rpt,1647,2017-04-06
.................\..............\......\top_module_drc_routed.pb,37,2017-04-06
.................\..............\......\top_module_drc_routed.rpt,3409,2017-04-06
.................\..............\......\top_module_io_placed.rpt,82357,2017-04-06
.................\..............\......\top_module_opt.dcp,600754,2017-04-06
.................\..............\......\top_module_placed.dcp,989827,2017-04-06
.................\..............\......\top_module_power_routed.rpt,7784,2017-04-06
.................\..............\......\top_module_power_summary_routed.pb,676,2017-04-06
.................\..............\......\top_module_routed.dcp,1218853,2017-04-06
.................\..............\......\top_module_route_status.pb,44,2017-04-06
.................\..............\......\top_module_route_status.rpt,588,2017-04-06
.................\..............\......\top_module_timing_summary_routed.rpt,105760,2017-04-06
.................\..............\......\top_module_timing_summary_routed.rpx,100420,2017-04-06
.................\..............\......\top_module_utilization_placed.pb,233,2017-04-06
.................\..............\......\top_module_utilization_placed.rpt,9199,2017-04-06
.................\..............\......\vivado.jou,734,2017-04-06
.................\..............\......\vivado.pb,149,2017-04-06
.................\..............\......\vivado_4524.backup.jou,710,2017-03-30
.................\..............\......\vivado_6620.backup.jou,734,2017-03-31
.................\..............\......\write_bitstream.pb,4809,2017-04-06
.................\..............\synth_1
.................\..............\.......\.vivado.begin.rst,180,2017-04-06
.................\..............\.......\.vivado.end.rst,0,2017-04-06
.................\..............\.......\.Vivado_Synthesis.queue.rst,0,2017-04-06
.................\..............\.......\fsm_encoding.os,1790,2017-04-06
.................\..............\.......\gen_run.xml,6041,2017-04-06
.................\..............\.......\htr.txt,381,2017-04-06
.................\..............\.......\ISEWrap.js,7308,2017-04-06
.................\..............\.......\ISEWrap.sh,1622,2017-04-06
.................\..............\.......\rundef.js,1261,2017-04-06
.................\..............\.......\runme.bat,229,2017-04-06
.................\..............\.......\runme.log,56357,2017-04-06
.................\..............\.......\runme.sh,1141,2017-04-06
.................\..............\.......\top_module.dcp,733118,2017-04-06
.................\..............\.......\top_module.tcl,2635,2017-04-06
.................\..............\.......\top_module.vds,55929,2017-04-06
.................\..............\.......\top_module_utilization_synth.pb,233,2017-04-06
.................\..............\.......\top_module_utilization_synth.rpt,7100,2017-04-06
.................\..............\.......\vivado.jou,730,2017-04-06
.................\..............\.......\vivado.pb,98121,2017-04-06
.................\project_4.sim