-
凤凰变色坐骑
说明: 问道SF最新版本的坐骑,变色凤凰,弄了好多种颜色,微变服务器直接用,原版的话,需要修改下坐骑能力,非常简单(Ask SF about the latest version of the mount, discolored Phoenix, made a variety of colors, slightly change the server to use directly, the original version, need to modify the mount ability, very simple.)
- 2020-06-17 07:00:02下载
- 积分:1
-
MMC9
9电平MMC逆变器,开环控制,明显可以看出9电平逆变,采用载波移相调制(9-level MMC Inverter, Open-loop)
- 2020-09-06 10:38:04下载
- 积分:1
-
AMIBIOS8_AMI_Firmware_Update_Utility
use this tool to update your ami bios. think it can use to fix serial number error, etc. i got this from googling. hope someone can be help by this.
- 2020-12-05 04:19:23下载
- 积分:1
-
laoshi
说明: 实现OCR光学识别,可识别数字英文字母,进一步编辑可实现文字的识别(Realization of OCR optical recognition)
- 2020-06-24 17:37:19下载
- 积分:1
-
ENGINEERING_OPTICS_WITH_MATLAB
Ebook about fourier optics
- 2011-06-08 02:46:34下载
- 积分:1
-
peizhun
//以上的代码加载了两个PCD文件得到共享指针,
//后续配准是完成对源点云到目标点云的参考坐标系的变换矩阵的估计,
//得到第二组点云变换到第一组点云坐标系下的变换矩阵
// 将输入的扫描点云数据过滤到原始尺寸的10%以提高匹配的速度,
//只对源点云进行滤波,减少其数据量,而目标点云不需要滤波处理
//因为在NDT算法中在目标点云 对应的 体素网格数据结构的 统计计算不使用单个点,
//而是使用包含在每个体素单元格中的点的统计数据(The following links describe a set of basic PCL tutorials. Please note that their source codes may already be provided as part of the PCL regular releases, so check there before you start copy & pasting the code. The list of tutorials below is automatically generated from reST files located in our git repository.)
- 2019-04-01 11:00:00下载
- 积分:1
-
谐波电流检测仿真
三相桥式不控整流主电路仿真模型,根据控制框图搭建交流测谐波电流检测模块,并给出检测所得谐波电流的波形(Based on the simulation model of three-phase bridge uncontrolled rectifier main circuit, the detection module of AC harmonic current is built according to the control block diagram, and the waveform of harmonic current is given.)
- 2018-10-11 12:04:15下载
- 积分:1
-
PB do with a small library management system without the installation procedure...
用PB做的一个小型图书管理系统 无安装程序ASA数据库-PB do with a small library management system without the installation procedure ASA databases
- 2022-05-23 11:31:14下载
- 积分:1
-
时钟由Verilog可计数从00:00至23:59写作。带一个文件到…
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
- 2022-10-19 21:25:03下载
- 积分:1
-
开发人员面试评估表
这是一个开发人员面试评估表,希望大家用得上的。(Developer Interview Assessment Form)
- 2020-06-22 05:00:02下载
- 积分:1