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代码说明：

  vivado2017.4下的串口通信的Verilog源码，一次传输8位，包括发送模块，接受模块，顶层模块(Verilog source code for serial communication under vivado 2017.4, which transmits 8 bits at a time, including sending module, receiving module and top module)

文件列表：

uart_rs.v, 4127 , 2019-07-03
uart_ts.v, 3389 , 2019-07-03
uart.v, 1329 , 2019-07-05