Vhdl_testbench

代码说明：

  vhdl 的testbench编写教程，英文ppt以及源码工程(Write tutorials, as well as English ppt Source of engineering vhdl testbench)

文件列表：

vhdl_testbench
..............\db
..............\..\altsyncram_94d1.tdf,49666,2010-11-25
..............\..\altsyncram_mqc1.tdf,13377,2010-12-12
..............\..\altsyncram_psc1.tdf,12569,2010-11-25
..............\..\cmpr_9dc.tdf,1915,2010-12-12
..............\..\cmpr_hfc.tdf,1915,2010-11-25
..............\..\cntr_79h.tdf,3379,2010-11-25
..............\..\cntr_9nf.tdf,4049,2010-12-12
..............\..\cntr_hpf.tdf,3702,2010-11-25
..............\..\cntr_v6h.tdf,3981,2010-12-12
..............\..\example_vhdl_testbench_design.amm.cdb,459,2010-12-12
..............\..\example_vhdl_testbench_design.asm.qmsg,3128,2010-12-12
..............\..\example_vhdl_testbench_design.asm.rdb,1539,2010-12-12
..............\..\example_vhdl_testbench_design.asm_labs.ddb,39428,2010-12-12
..............\..\example_vhdl_testbench_design.cbx.xml,261,2010-12-12
..............\..\example_vhdl_testbench_design.cmp.bpm,701,2010-12-12
..............\..\example_vhdl_testbench_design.cmp.cdb,9669,2010-12-12
..............\..\example_vhdl_testbench_design.cmp.hdb,13649,2010-12-12
..............\..\example_vhdl_testbench_design.cmp.kpt,213,2010-12-12
..............\..\example_vhdl_testbench_design.cmp.logdb,13696,2010-12-12
..............\..\example_vhdl_testbench_design.cmp.rdb,27274,2010-12-12
..............\..\example_vhdl_testbench_design.cmp_merge.kpt,219,2010-12-12
..............\..\example_vhdl_testbench_design.db_info,138,2010-12-11
..............\..\example_vhdl_testbench_design.eda.qmsg,5848,2010-12-12
..............\..\example_vhdl_testbench_design.fit.qmsg,43470,2010-12-12
..............\..\example_vhdl_testbench_design.hier_info,11523,2010-12-12
..............\..\example_vhdl_testbench_design.hif,5735,2010-12-12
..............\..\example_vhdl_testbench_design.idb.cdb,1892,2010-12-12
..............\..\example_vhdl_testbench_design.lpc.html,3018,2010-12-12
..............\..\example_vhdl_testbench_design.lpc.rdb,586,2010-12-12
..............\..\example_vhdl_testbench_design.lpc.txt,3216,2010-12-12
..............\..\example_vhdl_testbench_design.map.bpm,675,2010-12-12
..............\..\example_vhdl_testbench_design.map.cdb,3957,2010-12-12
..............\..\example_vhdl_testbench_design.map.hdb,13262,2010-12-12
..............\..\example_vhdl_testbench_design.map.kpt,721,2010-12-12
..............\..\example_vhdl_testbench_design.map.logdb,4,2010-12-12
..............\..\example_vhdl_testbench_design.map.qmsg,13330,2010-12-12
..............\..\example_vhdl_testbench_design.map_bb.cdb,1108,2010-12-12
..............\..\example_vhdl_testbench_design.map_bb.hdb,10309,2010-12-12
..............\..\example_vhdl_testbench_design.map_bb.logdb,4,2010-12-12
..............\..\example_vhdl_testbench_design.piranha_io_sim_cache.ff_ff_0c_fast.hsd,293111,2010-12-12
..............\..\example_vhdl_testbench_design.piranha_io_sim_cache.tt_tt_0c_slow.hsd,290063,2010-12-12
..............\..\example_vhdl_testbench_design.piranha_io_sim_cache.tt_tt_85c_slow.hsd,294430,2010-12-12
..............\..\example_vhdl_testbench_design.pre_map.cdb,6826,2010-12-12
..............\..\example_vhdl_testbench_design.pre_map.hdb,17000,2010-12-12
..............\..\example_vhdl_testbench_design.rtlv.hdb,16973,2010-12-12
..............\..\example_vhdl_testbench_design.rtlv_sg.cdb,9066,2010-12-12
..............\..\example_vhdl_testbench_design.rtlv_sg_swap.cdb,1675,2010-12-12
..............\..\example_vhdl_testbench_design.sgdiff.cdb,3539,2010-12-12
..............\..\example_vhdl_testbench_design.sgdiff.hdb,15781,2010-12-12
..............\..\example_vhdl_testbench_design.sld_design_entry.sci,197,2010-12-12
..............\..\example_vhdl_testbench_design.sld_design_entry_dsc.sci,197,2010-12-12
..............\..\example_vhdl_testbench_design.smart_action.txt,8,2010-12-12
..............\..\example_vhdl_testbench_design.sta.qmsg,23546,2010-12-12
..............\..\example_vhdl_testbench_design.sta.rdb,8780,2010-12-12
..............\..\example_vhdl_testbench_design.sta_cmp.4_slow_900mv_85c.tdb,10872,2010-12-12
..............\..\example_vhdl_testbench_design.syn_hier_info,0,2010-12-12
..............\..\example_vhdl_testbench_design.tiscmp.fastest_slow_900mv_0c.ddb,285681,2010-12-12
..............\..\example_vhdl_testbench_design.tiscmp.fastest_slow_900mv_85c.ddb,285787,2010-12-12
..............\..\example_vhdl_testbench_design.tiscmp.fast_900mv_0c.ddb,311948,2010-12-12
..............\..\example_vhdl_testbench_design.tiscmp.slow_900mv_0c.ddb,315223,2010-12-12
..............\..\example_vhdl_testbench_design.tiscmp.slow_900mv_85c.ddb,315030,2010-12-12
..............\..\example_vhdl_testbench_design.tis_db_list.ddb,231,2010-12-12
..............\..\logic_util_heursitic.dat,3432,2010-12-12
..............\..\prev_cmp_example_vhdl_testbench_design.qmsg,4389,2010-11-25
..............\..\shift_taps_3o21.tdf,3073,2010-11-25
..............\..\shift_taps_lb21.tdf,2933,2010-12-12
..............\..\shift_taps_rf21.tdf,3056,2010-11-25
..............\example_vhdl.vhd,977,2010-11-25
..............\example_vhdl.vhd.bak,954,2010-11-25
..............\example_vhdl_testbench_design.qpf,1351,2010-11-25
..............\example_vhdl_testbench_design.qsf,6007,2010-12-24
..............\example_vhdl_testbench_design_assignment_defaults.qdf,48544,2010-12-11
..............\greybox_tmp
..............\...........\cbx_args.txt,256,2010-12-11
..............\incremental_db
..............\..............\compiled_partitions
..............\..............\...................\example_vhdl_testbench_design.db_info,138,2010-12-11
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.cbp,193,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.cdb,5175,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.dfp,33,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.hdb,13357,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.kpt,199,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.logdb,4,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.rcfdb,4963,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.cmp.re.rcfdb,5189,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.map.cdb,3721,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.map.dpi,1517,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.map.hdb,13544,2010-12-12
..............\..............\...................\example_vhdl_testbench_design.root_partition.map.kpt,724,2010-12-12
..............\..............\htm" target=_blank>README,653,2010-11-25
..............\modelsim_vhdl_testbench.wrf,6800866,2010-12-23
..............\output_files
..............\............\example_vhdl_testbench_design.archive.rpt,3732,2010-11-25
..............\............\example_vhdl_testbench_design.asm.rpt,9794,2010-12-12
..............\............\example_vhdl_testbench_design.done,26,2010-12-12
..............\............\example_vhdl_testbench_design.eda.rpt,8338,2010-12-12
..............\............\example_vhdl_testbench_design.fit.rpt,243821,2010-12-12
..............\............\example_vhdl_testbench_design.fit.smsg,499,2010-12-12