fir_vivado

代码说明：

  此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari)

文件列表：

fir_vivado
..........\coe
..........\...\fir_coef_for_coe.coe,282,2016-07-21
..........\...\signal_for_coe.coe,5221,2016-07-21
..........\ip
..........\..\xilinx_com_hls_fir_top_1_0
..........\..\..........................\component.xml,37326,2016-07-21
..........\..\..........................\constraints
..........\..\..........................\...........\fir_top_ooc.xdc,455,2016-07-21
..........\..\..........................\doc
..........\..\..........................\...\ReleaseNotes.txt,416,2016-07-21
..........\..\..........................\hdl
..........\..\..........................\...\verilog
..........\..\..........................\...\.......\fir_top.v,15411,2016-07-21
..........\..\..........................\...\.......\fir_top_mac_muladd_11s_11s_32ns_32_1.v,1433,2016-07-21
..........\..\..........................\...\.......\fir_top_signal_input_tmp.v,1484,2016-07-21
..........\..\..........................\...\vhdl
..........\..\..........................\...\....\fir_top.vhd,24647,2016-07-21
..........\..\..........................\...\....\fir_top_mac_muladd_11s_11s_32ns_32_1.vhd,2338,2016-07-21
..........\..\..........................\...\....\fir_top_signal_input_tmp.vhd,3245,2016-07-21
..........\..\..........................\misc

..........\..\..........................\xgui
..........\..\..........................\....\fir_top_v1_0.tcl,353,2016-07-21
..........\project_1
..........\.........\ip_upgrade.log,5993,2016-07-21
..........\.........\project_1.cache
..........\.........\...............\compile_simlib
..........\.........\...............\..............\activehdl
..........\.........\...............\..............\ies
..........\.........\...............\..............\modelsim
..........\.........\...............\..............\questa
..........\.........\...............\..............\riviera
..........\.........\...............\..............\vcs
..........\.........\...............\ip
..........\.........\...............\..\18f946c7a707cdac
..........\.........\...............\..\................\18f946c7a707cdac.xci,6210,2016-07-20
..........\.........\...............\..\................\dbg_hub_CV.dcp,230718,2016-07-20
..........\.........\...............\..\1cda5d1f3030c29d
..........\.........\...............\..\................\1cda5d1f3030c29d.xci,397722,2016-07-20
..........\.........\...............\..\................\u_ila_0_CV.dcp,1191517,2016-07-20
..........\.........\...............\..\5a8a90343563d760
..........\.........\...............\..\................\5a8a90343563d760.xci,397723,2016-07-20
..........\.........\...............\..\................\u_ila_0_CV.dcp,1346953,2016-07-20
..........\.........\...............\..\61eab77951af087f
..........\.........\...............\..\................\61eab77951af087f.xci,397723,2016-07-20
..........\.........\...............\..\................\u_ila_0_CV.dcp,2489509,2016-07-20
..........\.........\...............\..\a4ad0e26a216f6a9
..........\.........\...............\..\................\a4ad0e26a216f6a9.xci,397723,2016-07-22
..........\.........\...............\..\................\u_ila_0_CV.dcp,1262009,2016-07-22
..........\.........\...............\..\b18ba793aeb623f1
..........\.........\...............\..\................\b18ba793aeb623f1.xci,397723,2016-07-20
..........\.........\...............\..\................\u_ila_0_CV.dcp,1254009,2016-07-20
..........\.........\...............\wt
..........\.........\...............\..\java_command_handlers.wdf,29021,2016-09-01
..........\.........\...............\..\project.wpc,123,2016-09-01
..........\.........\...............\..\synthesis.wdf,5232,2016-07-27
..........\.........\...............\..\synthesis_details.wdf,100,2016-07-27
..........\.........\...............\..\webtalk_pa.xml,19429,2016-09-01
..........\.........\...............\..\xsim.wdf,256,2016-07-27
..........\.........\project_1.hw
..........\.........\............\hw_1
..........\.........\............\....\hw.xml,48147,2016-09-01
..........\.........\............\....\layout
..........\.........\............\....\......\hw_ila_1.layout,245343,2016-09-01
..........\.........\............\....\wave
..........\.........\............\....\....\hw_ila_data_1
..........\.........\............\....\....\.............\hw_ila_data_1.wcfg,2478,2016-09-01
..........\.........\............\....\....\.............\hw_ila_data_1.wdb,5989,2016-09-01
..........\.........\............\project_1.lpr,343,2016-07-20
..........\.........\project_1.ip_user_files
..........\.........\.......................\bd
..........\.........\.......................\..\design_1
..........\.........\.......................\..\........\hdl
..........\.........\.......................\..\........\...\design_1.v,4543,2016-07-27
..........\.........\.......................\..\........\ip
..........\.........\.......................\..\........\..\design_1_blk_mem_gen_0_0
..........\.........\.......................\..\........\..\........................\sim
..........\.........\.......................\..\........\..\........................\...\design_1_blk_mem_gen_0_0.v,6392,2016-07-27
..........\.........\.......................\..\........\..\design_1_blk_mem_gen_1_0
..........\.........\.......................\..\........\..\........................\sim
..........\.........\.......................\..\........\..\........................\...\design_1_blk_mem_gen_1_0.v,6379,2016-07-27
..........\.........\.......................\..\........\..\design_1_blk_mem_gen_2_1
..........\.........\.......................\..\........\..\........................\sim
..........\.........\.......................\..\........\..\........................\...\design_1_blk_mem_gen_2_1.v,7003,2016-07-27
..........\.........\.......................\..\........\..\design_1_fir_top_0_0
..........\.........\.......................\..\........\..\....................\sim
..........\.........\.......................\..\........\..\....................\...\design_1_fir_top_0_0.v,4802,2016-07-27
..........\.........\.......................\..\........\..\design_1_xlconstant_0_0
..........\.........\.......................\..\........\..\.......................\sim
..........\.........\.......................\..\........\..\.......................\...\design_1_xlconstant_0_0.v,2547,2016-07-27
..........\.........\.......................\..\........\ipshared
..........\.........\.......................\..\........\........\xilinx.com
..........\.........\.......................\..\........\........\..........\xlconstant_v1_1
..........\.........\.......................\..\........\........\..........\...............\xlconstant.v,857,2016-07-27
..........\.........\.......................\ip
..........\.........\.......................\..\clk_wiz_0
..........\.........\.......................\..\.........\clk_wiz_0.veo,3608,2016-07-27
..........\.........\.......................\..\.........\clk_wiz_0_stub.v,1231,2016-07-21
..........\.........\.......................\..\.........\clk_wiz_0_stub.vhdl,1199,2016-07-21