CPU-Verilog
代码说明:
说明: 简单流水线CPU,使用 verilog实现,实现一条指令的整个流程(Implementation of Simple Pipeline CPU Verilog)
文件列表:
new\defines.v, 2613 , 2014-02-24
new\ex.v, 5625 , 2014-02-24
new\ex_mem.v, 2976 , 2014-02-24
new\hilo_reg.v, 2431 , 2019-07-15
new\id.v, 10042 , 2019-07-15
new\id_ex.v, 2955 , 2014-02-20
new\if_id.v, 2363 , 2014-02-20
new\inst_rom.data, 144 , 2014-02-25
new\inst_rom.v, 2339 , 2014-03-30
new\mem.v, 2865 , 2014-02-24
new\mem_wb.v, 2968 , 2014-02-24
new\openmips.v, 7251 , 2019-07-15
new\openmips_min_sopc.v, 2699 , 2014-03-30
new\openmips_min_sopc_tb.v, 2348 , 2014-02-22
new\pc_reg.v, 2364 , 2014-03-30
new\regfile.v, 3386 , 2014-02-07
new, 0 , 2019-07-15
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