Xilinx_ZCU102_Evaluation_Kit-master

代码说明：

说明：  Xilinx zcu102 开发板入门例子，可运行于vivado 2017.4 平台(Xilinx zcu102 development board introduction example, can run on vivado 2017.4 platform)

文件列表：

Xilinx_ZCU102_Evaluation_Kit-master, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\README.md, 83 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache\wt, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache\wt\gui_handlers.wdf, 4924 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache\wt\java_command_handlers.wdf, 2205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache\wt\project.wpc, 117 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache\wt\synthesis.wdf, 5361 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache\wt\synthesis_details.wdf, 97 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.cache\wt\webtalk_pa.xml, 5428 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.hw, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.hw\hw_1, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.hw\hw_1\hw.xml, 772 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.hw\runLed.lpr, 335 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_1.xml, 205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_10.xml, 205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_11.xml, 205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_12.xml, 219 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_13.xml, 226 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_14.xml, 205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_15.xml, 219 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_16.xml, 226 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_17.xml, 205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_18.xml, 219 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_19.xml, 226 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_2.xml, 219 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_3.xml, 226 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_4.xml, 205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_5.xml, 219 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_6.xml, 226 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_7.xml, 205 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_8.xml, 219 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\.jobs\vrs_config_9.xml, 226 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.Vivado_Implementation.queue.rst, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.init_design.begin.rst, 174 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.init_design.end.rst, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.opt_design.begin.rst, 174 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.opt_design.end.rst, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.place_design.begin.rst, 174 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.place_design.end.rst, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.route_design.begin.rst, 174 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.route_design.end.rst, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.vivado.begin.rst, 346 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.vivado.end.rst, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.write_bitstream.begin.rst, 174 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\.write_bitstream.end.rst, 0 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\ISEWrap.js, 7306 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\ISEWrap.sh, 1623 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\gen_run.xml, 5996 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\htr.txt, 388 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\init_design.pb, 2823 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\opt_design.pb, 8725 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\place_design.pb, 13131 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\project.wdf, 3603 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\route_design.pb, 12652 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed.bit, 26510893 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed.dcp, 398401 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed.tcl, 2279 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed.vdi, 26718 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_10592.backup.vdi, 22810 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_12168.backup.vdi, 22707 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_2128.backup.vdi, 22805 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_3416.backup.vdi, 22705 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_8700.backup.vdi, 22841 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_9500.backup.vdi, 22809 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_bus_skew_routed.pb, 30 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_bus_skew_routed.rpt, 919 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_bus_skew_routed.rpx, 1034 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_clock_utilization_routed.rpt, 26032 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_control_sets_placed.rpt, 3082 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_drc_opted.pb, 37 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_drc_opted.rpt, 1253 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_drc_opted.rpx, 97 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_drc_routed.pb, 37 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_drc_routed.rpt, 1257 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_drc_routed.rpx, 98 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_io_placed.rpt, 394486 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_methodology_drc_routed.pb, 52 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_methodology_drc_routed.rpt, 13949 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_methodology_drc_routed.rpx, 20798 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_opt.dcp, 397052 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_placed.dcp, 431110 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_power_routed.rpt, 9135 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_power_routed.rpx, 46564 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_power_summary_routed.pb, 722 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_route_status.pb, 44 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_route_status.rpt, 588 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_routed.dcp, 444661 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_timing_summary_routed.pb, 52 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_timing_summary_routed.rpt, 7528 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_timing_summary_routed.rpx, 11697 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_utilization_placed.pb, 258 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runLed_utilization_placed.rpt, 10117 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\rundef.js, 1170 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runme.bat, 219 , 2018-09-18
Xilinx_ZCU102_Evaluation_Kit-master\runLed\runLed.runs\impl_1\runme.log, 26098 , 2018-09-18