445.FPGA CNN

代码说明：

说明：  vhdl cnn 您的帐号尚未开通，请上传编程资料开通或在线付费马上开通(vhdl cnnCategory: verilog All Download: FPGA_Based_CNN-master.zipSize:2.30 MB FavoriteFavorite Preview code View comments Description family:-app...)

文件列表：

FPGA CNN\FPGA CNN\alenxnet_verilog.pdf, 466504 , 2018-06-11
FPGA CNN\FPGA CNN\BNN.pdf, 648842 , 2017-12-25
FPGA CNN\FPGA CNN\c_ug1046-ultrafast-design-methodology-guide.pdf, 4589324 , 2017-12-25
FPGA CNN\FPGA CNN\eame-2015-xilinx-paper-v1-8.pdf, 527901 , 2017-12-25
FPGA CNN\FPGA CNN\farabet-suml-11.pdf, 691701 , 2017-12-25
FPGA CNN\FPGA CNN\FPGA -CNN 存储加速.pdf, 611295 , 2018-01-07
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\config, 301 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\description, 73 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\HEAD, 23 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\applypatch-msg.sample, 478 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\commit-msg.sample, 896 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\fsmonitor-watchman.sample, 3505 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\post-update.sample, 189 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\pre-applypatch.sample, 424 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\pre-commit.sample, 1642 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\pre-push.sample, 1348 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\pre-rebase.sample, 4898 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\pre-receive.sample, 544 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\prepare-commit-msg.sample, 1492 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\hooks\update.sample, 3610 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\index, 10929 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\info\exclude, 240 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\logs\HEAD, 186 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\logs\refs\heads\master, 186 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\logs\refs\remotes\origin\HEAD, 186 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\objects\pack\pack-cf3d9fb2b386aba43a2acac1ee0588bbe6046059.idx, 4740 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\objects\pack\pack-cf3d9fb2b386aba43a2acac1ee0588bbe6046059.pack, 2284029 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\packed-refs, 114 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\refs\heads\master, 41 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.git\refs\remotes\origin\HEAD, 32 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\.gitignore, 212 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\.qsys_edit\filters.xml, 68 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\.qsys_edit\mem_system.xml, 85132 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\.qsys_edit\mem_system_schematic.nlv, 31228 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\.qsys_edit\pcie_system.xml, 85577 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\.qsys_edit\pcie_system_schematic.nlv, 0 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\.qsys_edit\preferences.xml, 551 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\avalon_bridge.v, 3092 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\avalon_bridge_hw.tcl, 9111 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\bit_width.vh, 359 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\cent_ctrl.v, 20761 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\cent_ctrl_hw.tcl, 15308 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\clock.v, 88 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\Clock_hw.tcl, 2416 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\cnn_parameters.vh, 870 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\conv.v, 16411 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\conv_old.v, 15358 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.db_info, 144 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.sld_design_entry.sci, 227 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.dpf, 1365 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.htm, 36760 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qpf, 127 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qsf, 44148 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.SDC, 6809 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.sld, 600 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.v, 77475 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator_assignment_defaults.qdf, 55090 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\fifo_v2.qip, 434 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\fifo_v2.v, 6679 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\ifm_loader.v, 825 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\main_states.vh, 533 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\main_state_actions.v, 4750 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\main_state_machine.v, 3511 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\memory_export.v, 920 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\memory_export2.v, 2556 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\memory_export2_hw.tcl, 8405 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\memory_export_hw.tcl, 5871 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\mem_init.mif, 4779241 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\mem_system.qsys, 329440 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\mem_system.sopcinfo, 2926984 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\mem_system_mem_if_ddr3_emif_0_p0_all_pins.txt, 5990 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\mem_system_mem_if_ddr3_emif_0_p0_summary.csv, 2194 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\new_rtl_netlist, 206718 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\ofm_loader.v, 847 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\ofm_wb.v, 14175 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\old_rtl_netlist, 296863 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\parameters.vh, 241 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\pcie_system.qsys, 44230 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\pcie_system.sopcinfo, 2926898 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src\pll_reconfig_xcvr_clk_src_0002.qip, 368 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src\pll_reconfig_xcvr_clk_src_0002.v, 2179 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src.qip, 66111 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src.v, 17421 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\read_states.vh, 306 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\read_state_actions.v, 39162 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\rom_script.py, 1212 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\serv_req_info.txt, 6424 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\toSevenSeg.v, 684 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\DE5Net_Conv_Accelerator\weight_loader.v, 4091 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.altera_dma.ko.cmd, 324 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.altera_dma.mod.o.cmd, 27894 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.altera_dma.o.cmd, 42560 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.built-in.o.cmd, 201 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.goutputstream-0Y4HMY, 47154 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.goutputstream-2BLFMY, 47070 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.goutputstream-AXCMMY, 47837 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.goutputstream-O215MY, 60197 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.goutputstream-QK7EMY, 47828 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.goutputstream-QPOYMY, 127841 , 2018-03-16
FPGA CNN\FPGA CNN\FPGA_Based_CNN(verilog)\pcie_linux_driver\.goutputstream-RQCNMY, 46969 , 2018-03-16