dvb_fpga-master

代码说明：

说明：  DVB-S2发送程序,根据欧洲电信标准编写，信号的发送处理流程(DVB-S2 send fpga master)

文件列表：

dvb_fpga-master, 0 , 2020-01-30
dvb_fpga-master\.github, 0 , 2020-01-30
dvb_fpga-master\.github\workflows, 0 , 2020-01-30
dvb_fpga-master\.github\workflows\push.yml, 331 , 2020-01-30
dvb_fpga-master\.gitignore, 41 , 2020-01-30
dvb_fpga-master\.gitmodules, 132 , 2020-01-30
dvb_fpga-master\.hdl_checker.config, 299 , 2020-01-30
dvb_fpga-master\LICENSE, 35149 , 2020-01-30
dvb_fpga-master\README.md, 4538 , 2020-01-30
dvb_fpga-master\docker, 0 , 2020-01-30
dvb_fpga-master\docker\Dockerfile, 1046 , 2020-01-30
dvb_fpga-master\docker\docker_entry_point.sh, 1286 , 2020-01-30
dvb_fpga-master\docker\run_tests.sh, 1601 , 2020-01-30
dvb_fpga-master\gnuradio_data, 0 , 2020-01-30
dvb_fpga-master\gnuradio_data\Makefile, 1083 , 2020-01-30
dvb_fpga-master\gnuradio_data\dvbs2_frame_sync.grc, 72662 , 2020-01-30
dvb_fpga-master\gnuradio_data\dvbs2_tx.py, 15461 , 2020-01-30
dvb_fpga-master\misc, 0 , 2020-01-30
dvb_fpga-master\misc\system_architecture.png, 146175 , 2020-01-30
dvb_fpga-master\rtl, 0 , 2020-01-30
dvb_fpga-master\rtl\axi_baseband_scrambler.vhd, 3416 , 2020-01-30
dvb_fpga-master\rtl\axi_bch_encoder.vhd, 9388 , 2020-01-30
dvb_fpga-master\rtl\axi_bit_interleaver.vhd, 24557 , 2020-01-30
dvb_fpga-master\rtl\axi_stream_delay.vhd, 3208 , 2020-01-30
dvb_fpga-master\rtl\axi_stream_fifo.vhd, 5898 , 2020-01-30
dvb_fpga-master\rtl\axi_stream_master_adapter.vhd, 4727 , 2020-01-30
dvb_fpga-master\rtl\bch_encoder_mux.vhd, 8499 , 2020-01-30
dvb_fpga-master\rtl\bch_generated, 0 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_128x16.vhd, 54081 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_128x32.vhd, 97591 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_128x64.vhd, 194999 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_128x8.vhd, 34012 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_160x16.vhd, 69000 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_160x32.vhd, 123965 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_160x64.vhd, 245157 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_160x8.vhd, 41816 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_168x8.vhd, 42782 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_192x16.vhd, 78264 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_192x32.vhd, 144755 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_192x64.vhd, 276120 , 2020-01-30
dvb_fpga-master\rtl\bch_generated\bch_192x8.vhd, 48424 , 2020-01-30
dvb_fpga-master\rtl\common_pkg.vhd, 3885 , 2020-01-30
dvb_fpga-master\rtl\dvb_utils_pkg.vhd, 4310 , 2020-01-30
dvb_fpga-master\rtl\edge_detector.vhd, 2900 , 2020-01-30
dvb_fpga-master\rtl\ram_inference.vhd, 3631 , 2020-01-30
dvb_fpga-master\rtl\skidbuffer.vhd, 7144 , 2020-01-30
dvb_fpga-master\rtl\sr_delay.vhd, 3104 , 2020-01-30
dvb_fpga-master\rtl\synchronizer.vhd, 2754 , 2020-01-30
dvb_fpga-master\run.py, 14058 , 2020-01-30
dvb_fpga-master\testbench, 0 , 2020-01-30
dvb_fpga-master\testbench\axi_baseband_scrambler_tb.vhd, 8529 , 2020-01-30
dvb_fpga-master\testbench\axi_bch_encoder_tb.vhd, 10378 , 2020-01-30
dvb_fpga-master\testbench\axi_bit_interleaver_tb.vhd, 11425 , 2020-01-30
dvb_fpga-master\testbench\axi_file_compare_tb.vhd, 10079 , 2020-01-30
dvb_fpga-master\testbench\axi_file_reader_tb.vhd, 9839 , 2020-01-30
dvb_fpga-master\testbench\axi_stream_delay_tb.vhd, 7578 , 2020-01-30
dvb_fpga-master\testbench\utils, 0 , 2020-01-30
dvb_fpga-master\testbench\utils\axi_file_compare.vhd, 5970 , 2020-01-30
dvb_fpga-master\testbench\utils\axi_file_reader.vhd, 9886 , 2020-01-30
dvb_fpga-master\testbench\utils\file_dumper.vhd, 2037 , 2020-01-30
dvb_fpga-master\testbench\utils\file_utils_pkg.vhd, 8002 , 2020-01-30
dvb_fpga-master\testbench\utils\linked_list_pkg.vhd, 3688 , 2020-01-30
dvb_fpga-master\testbench\utils\testbench_utils_pkg.vhd, 6441 , 2020-01-30
dvb_fpga-master\third_party, 0 , 2020-01-30
dvb_fpga-master\third_party\hdl_string_format, 0 , 2020-01-30
dvb_fpga-master\wave.do, 1992 , 2020-01-30