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MIPI Alliance Specification for D-PHY
MIPI Alliance Specification for D-PHY Version 1.00.00 – 14 May 2009配合“MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)“ 一起看。http://download.csdn.net/detail/micro_st/4242724Version1.00.0014-May-2009MIPI Alliance Specification for D-PHY2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or3 controlled by any of the authors or developers of this material or MIPl. The material contained herein is4 provided on an"as iS basis and to the maximum extent permitted by applicable law, this material is5 provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIP6 hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not7 limited to, any (ifany)inplied warranties, duties or conditions of merchantability, of fitness for a8 particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of9 viruses, and of lack of negligence10 All materials contained herein are protected by copyright laws, and may not be reproduced, republisheddistributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express12 prior written permission of MIPI Alliance. MIPl, MIPI Alliance and the dotted rainbow arch and all related3 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and14 cannot be used without its express prior written permission15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET16 POSSESSION. CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH17 REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT.IN NO EVENT WILLI8 ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT9 OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE20 GOODS OR SERVICES. LOST PROFITS. LOSS OF USE. LOSS OF DATA OR ANY INCIDENTAL.21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER22 CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR23 ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH25 DAMAGES26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is27 further notified that MIPI: (a)does not evaluate, test or verify the accuracy, soundness or credibility of the28 contents of this Document;(b)does not monitor or enforce compliance with the contents of this Document29 and (c)does not certify, test, or in any manner investigate products or services or any claims of compliance30 with the contents of this Document. The use or implementation of the contents of this Document may31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any34 IPR or claims of IPR as respects the contents of this document or otherwise35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed36 MIPI Alliance. Inc37 c/o IEEE-ISTO38 445 Hoes lane39 Piscataway, NJ0885440 Alin: Board SecretaryCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY42 Contents43 Draft Version 1.00.00-14 May 2009441 Overview1451.2 Purpose.…..,.,.,,.,..472 Terminology…2.1 Definitions162.2 Abbreviations…172.3 Acronyms51 3 D-PHY Introduction523.1 Summary of Phy functionality533.2 Mandatory Functionality················2054 4 Architecture21554.1 Lane modules…564.2 Master and slave2254.3 High Frequency Clock Generation22584.4 Clock lane data lanes and the phy-Protocol interface.224.5 Selectable Lane Options·;····················234.6 Lane Module Types4.6.1 Unidirectional Data Lane…264.6.2 Bi-directional data lanes26634.6.3 Clock lane.274.7 Configurations….7654.7.1 Unidirectional Configurations............664.7.2Bi-Dal Half-Duplex Configurations674.7.3 Mixed Data Lane configurations32Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential111Ⅴ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY695.1Transmission Data Structure,………………………∴335.1.1Data unitsa勹5.1.2 Bit order Serialization and De-Serialization33725.1.3 Encoding and decoding735.1.4 Data Buffering,33745.2 Lane States and Line levels755.3 Operating Modes: Control, High-Speed, and Escape5. 4 High-Speed Data Transmission··········;·5. 41 Burst payload data785.4.2 Start-of-Transmission795.4.3End-of-transmission805.4.4 HS Data Transmission burst.365.5 Bi-directional data Lane turnaround5.6 Escape Mode41835.6.1Remote triggers42845.6.2 Low-Power data Transmission43855.6.3 Ultra-Low Power State865.6.4 Escape Mode State Machine43875.7 High-Speed Clock Transmission885. 8 Clock lane Ultra-Low Power State50959 Global Operation Timing Parameters.……5.10 System Power States56915.11 Initialization56925.12 Calibration5.13 Global Operation Flow Diagram57945.14 Data Rate Dependent Parameters(informative)955. 14.1 Parameters Containing Only UI values965. 14.2 Parameters Containing Time and Ul values59Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY5.14.3 Parameters Containing Only Time Values…………5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent6 Fault detection611006.1 Contention detection1016.2 Sequence Error Detection.……611026.2.1 SoT Error621036.2.2 SOT Sync Error1046.2.3 EoT Sync Error1056.2. 4 Escape Mode Entry Command error.1066.2.5 LP Transmission Sync error621076.2.6 False Control error1086.3 Protocol Watchdog Timers(informative)62l096.3.1 HS RX Timeout6.3.2HS TX Timeout………………·················+···:··:·················∴62l116.3.3Escape mode timeout62l126.3. 4 Escape Mode Silence Timeout6.3.5 Turnaround errors114 7 Interconnect and Lane Configuration.641157.1 Lane configuration1167.2 Boundary Conditions.....…647.3 Definitions………64l187.4S- parameter Specifications………….651197.5 Characterization Conditions207.6 nterconnect Specifications………1217.6.1 Differential characteristics1227. 6.2 Common-mode characteristics671237.6.3 Intra-Lane Cross-Coupling1247. 6. 4 Mode-Conversion limitsCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY1257.6.5 Inter-Lane Cross-Coupling671267. 6.6 Inter-Lane static skew1277.7 Driver and receiver Characteristics1287.7.1 Differential Characteristics1297. 7.2 Common-Mode characteristics1307.7.3 Mode-Conversion Limits1317.7.4 Inter-Lane Matching132 8 Electrical Characterislics701338.1 Driver characteristics1348.1.1 High-Speed Transmitter1358.1.2 Low-Power Transmitter1368.2 Receiver Characteristic·…············…·······…8301378.2.1 High-Speed Receiver801388.2.2Low- Power receiver.................….….821398.3 Line contention detection1408.4 Input Characteristics8441 9 High-Speed Data-Clock Timing1429.1 High-Speed Clock Timing861439.2 Forward High-Speed Data Transmission Timing871449.2.1 Data-Clock Timing Specifications1459.3 Reverse High-Speed Data Transmission Timing89146 10 Regulatory Requirements91147 Annex A Logical PHY-Protocol Inter face Description(informative)92148A 1 Signal Description149A 2 High-Speed Transmit from the Master Side150A3 High-Speed receive at the slave Sidel00151A 4 High-Speed Transmit from the Slave side152A.5 High-Speed Receive at the Master SideIOICopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY153A6 Low-Power Data Transmission102154A7 Low-Power Data Reception.103155A 8 Turn-around156 Annex B Interconnect Design Guidelines (informative)105157B. 1 Practical distances105158B 2 RF Frequency Bands: Interference.105B3 Transmission Line design160B4 Reference Layer.106161B 5 Printed-Circuit board106162B6 Flex-foils106163B 7 Series resistance106164B 8 Connectors106165 Annex C 8b9b Line Coding for D-PHY(normative)107166C 1 Line Coding Features...·············108167C.1.1Enabled Features for the Protocol108l68C 1. 2 Enabled Features for the Phy108169C2 Coding scheme170C 2.1 8b9b Coding Properties.....108171C 2.2 Data Codes: Basic Code Set……….109C.2.3 Comma Codes: Unique Exception Codes110173C 2.4 Control Codes: Regular Exception Codes…10174C.2.5 Complete Coding Scheme………175C 3 Operation with the D-PhY…11117yload: Data and Control177C.3.2 Details for Hs transmission………112178C.3.3 Details for LP Transmissionl12179C 4 Error Signal180C5 Extended PplCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialⅤ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHYl81C.6 Complete Code Set.….….l15182Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidentialv111Version1.00.0014-May-2009MIPI Alliance Specification for D-PHYl83Figures184 Figure 1 Universal Lane Module functions21185 Figure2 Two Data Lane PHY Configuration.…………23186 Figure 3 Option Selection Flow Graph4187 Figure 4 Universal Lane Module Architecture25188 Figure 5 Lane Symbol Macros and Symbols Legend189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane190 Figure 7 Unidirectional Single Data Lane Configuration30191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT∴.30192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31193 Figure 10 Bidirectional Single Data Lane Configuration31194 Figure 1l Bi-directional Multiple Data Lane Configuration......32195 Figure 12 Mixed Type multiple data Lane Configuration32196 Figure 13 Line level34197 Figure 14 High-Speed Data Transmission in Bursts36198 Figure 15 TX and rX State Machines for High-Speed Data Transmission37Figure16 Turnaround Procedure.……39200 Figure 17 Turnaround State Machine40201 Figure 18 Trigger-Reset Command in Escape Mode202 Figure 19 Two Data Byte Low-Power Data Transmission Example203 Figure 20 Escape Mode State Machine204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47205 Figure 22 High-Speed Clock Transmission State Machine49206 Figure 23 Clock Lane Ultra-Low Power State State Machine········+·+···+·4···207 Figure 24 Data Lane Module State Diagram57208 Figure 25 Clock Lane Module state diagram58209 Figure 26 Point-to-point InterconnectCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential
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关于支持向量机里面讲核函数的，介绍了线性核函数、高斯核函数、及多项式核函数等。还介绍了核函数的判定以及Mercer定理1x1121T3212T42.3p(a)L313x2.3.32cT1V2C.223+d更一般地,核数K(x2z)=(xz+)“对应的映射后特征维度为a(求解方法参见http://zhidao.baiducom/question/16706714.html)由于计算的是内积,我们可以想到IR中的余弦相似度,如果ⅹ和z向量夹角越小,那么核函数值越大,反之,越小。因此,核函数值是(x)和(z)的相似度。再看另外一个核函数K(r, z)=expz-z|222这时,如果x和z很相近(x-2‖≈0),那么核函数值为1,如果x和z相差很大(x-2》0),那么核函数值约等于0。由于这个函数类似于高斯分布,因此称为高斯核函数,也叫做径向基函数( Radial basis function简称RBF)。它能够把原始特征映射到无穷维。既然高斯核函数能够比较ⅹ和z的相似度,并映射到0到1,回想 logistic回归, sigmoid函数可以,因此还有sigmoid核函数等等下面有张图说明在低维线性不可分时,映射到高维后就可分了,使用高斯核函数。Linear回回看目即Gaussian来自 Eric Xing的sdes注意,使用核函数后,怎么分类新来的样本呢?线性的时候我们使用SVM学与出W和b,新来样木ⅹ的话,我们使用wTx+ b来判断,如果值大于等于1,那么是正类,小于等于是负类。在两者之间,认为无法确定。如果使用了核函数后,W2x+b就变成了wφ(x)+b,是否先要找到p(x),然后再预测?答案背定不是了,找φ(x很麻烦,回想我们之前说过的wa+6=boy(0)x+bi=1(x(,x)+b只需将替换成(x,x),然后值的判断同上8核函数有效性判定问题:给定一个函数K,我们能否使用K来替代计算φ(x)2中(z),也就说,是否能够找出一个,使得对丁所有的x和z,都有k(x,2)=(x)r中(2)9比如给出了K(x,2)=(x2)2,是否能够认为K是一个有效的核函数下面来解决这个问题,给定m个训练样本全(r(3xm,每一个对应一个特征向量。那么,我们可以将(e) yJ仟意两个和带入K中,计算得到=0。I可以从1到m,j以从1到m,这样可以计算出m*m的核函数矩阵( Kernel Matrix)。为了方便,我们将核函数矩阵和(x,z)都使用K来表示如果假设K是有效地核函数,那么根据核函数定义k1=K(x0x0)=p(x()p(x0)=p(x(0)p(x()=K(x(,x)=K可见,矩阵K应该是个对称阵。让我们得出一个更强的结论,首先使用符号中x(x)来表示映射函数中(x)的第k维属性值。那么对于任意向量z,得2K2=∑∑2K3∑∑(m0y(0)2∑∑∑(z0)(x0)z∑∑∑29(x)k(z0)k i j=S|∑zipk(c(ak0.最后一步和前面计算K(x)=(x2)时类似。从这个公式我们可以看出,如果K是个有效的核函数(即K(xz)和(x)p(2)等价),那么,在训练集上得到的核函数矩阵K应该是半正定的(K≥0这样我们得到一个核函数的必要条件:K是有效的核函数==>核函数矩阵K是对称半正定的可幸的是,这个条件也是充分的,由 Mercer定理来表达。Mercer定理:如果函数K是×四→巫上的映射(也就是从两个n维向量映射到实数域)。那么如果K是一个有效核函数(也称为 Mercer核函数),那么当且仅当对于训练样例(r()x(m,其相应的核函数矩阵是对称半正定的。Mercer定理表明为了证明K是有效的核函数,那么我们不用去寻找φ,而只需要在训练集上求出各,然后判断矩阵K是否是半正定(使用左上角主子式大于等于零等方法)即可。许多其他的教科书在 Mercer定理证明过程中使用了范数和再生希尔伯特空间等概念,但在特征是n维的情况下,这里给出的证明是等价的。核函数不仅仅用在SWM上,但凡在一个模型后算法中出现了,我们都可以常使用区(xz)去替换,这可能能够很好地改善我们的算法。posted on2011-03-1820:22 Jerry Lead阅读(…)评论(…)编辑收藏刷新评论刷新页面返回顶部博客园首页博问新闻闪存程序员招聘知识库Powered by:博客园 Copyright@ Jerry Lead
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