verilog-ethernet

代码说明：

说明：  Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.

文件列表：

verilog-ethernet-master, 0 , 2020-10-06
verilog-ethernet-master\.gitignore, 33 , 2020-10-06
verilog-ethernet-master\.travis.yml, 443 , 2020-10-06
verilog-ethernet-master\AUTHORS, 40 , 2020-10-06
verilog-ethernet-master\COPYING, 1062 , 2020-10-06
verilog-ethernet-master\README, 9 , 2020-10-06
verilog-ethernet-master\README.md, 20452 , 2020-10-06
verilog-ethernet-master\example, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\Makefile, 402 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\README.md, 731 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\common, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\common\vivado.mk, 4094 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\fpga.xdc, 15819 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\fpga, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\fpga\Makefile, 4977 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\ip, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\ip\gtwizard_ultrascale_0.tcl, 999 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\lib, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\lib\eth, 12 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\rtl, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\rtl\debounce_switch.v, 2576 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\rtl\fpga.v, 25205 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\rtl\fpga_core.v, 21502 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\rtl\sync_signal.v, 1743 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\arp_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\axis_ep.py, 24 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\eth_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\ip_ep.py, 22 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\test_fpga_core.py, 17596 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\test_fpga_core.v, 7296 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\udp_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_10g\tb\xgmii_ep.py, 25 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\Makefile, 402 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\README.md, 731 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\common, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\common\vivado.mk, 4094 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\fpga.xdc, 15795 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\fpga, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\fpga\Makefile, 4977 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\ip, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\ip\gtwizard_ultrascale_0.tcl, 1001 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\lib, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\lib\eth, 12 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\rtl, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\rtl\debounce_switch.v, 2576 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\rtl\fpga.v, 25903 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\rtl\fpga_core.v, 21504 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\rtl\sync_signal.v, 1743 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb, 0 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\arp_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\axis_ep.py, 24 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\eth_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\ip_ep.py, 22 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\test_fpga_core.py, 17596 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\test_fpga_core.v, 7296 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\udp_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ADM_PCIE_9V3\fpga_25g\tb\xgmii_ep.py, 25 , 2020-10-06
verilog-ethernet-master\example\ATLYS, 0 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga, 0 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\Makefile, 402 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\clock.ucf, 325 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\common, 0 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\common\xilinx.mk, 6093 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\fpga.ucf, 12656 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\fpga, 0 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\fpga\Makefile, 1994 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\lib, 0 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\lib\eth, 12 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\rtl, 0 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\rtl\debounce_switch.v, 2576 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\rtl\fpga.v, 4419 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\rtl\fpga_core.v, 17973 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\rtl\sync_signal.v, 1743 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb, 0 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\arp_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\axis_ep.py, 24 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\eth_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\gmii_ep.py, 24 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\ip_ep.py, 22 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\test_fpga_core.py, 9484 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\test_fpga_core.v, 2692 , 2020-10-06
verilog-ethernet-master\example\ATLYS\fpga\tb\udp_ep.py, 23 , 2020-10-06
verilog-ethernet-master\example\AU200, 0 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g, 0 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\Makefile, 402 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\README.md, 820 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\common, 0 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\common\vivado.mk, 4094 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\fpga.xdc, 17390 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\fpga, 0 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\fpga\Makefile, 4787 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\ip, 0 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\ip\gtwizard_ultrascale_0.tcl, 1015 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\lib, 0 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\lib\eth, 12 , 2020-10-06
verilog-ethernet-master\example\AU200\fpga_10g\rtl, 0 , 2020-10-06