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高考志愿 填报综合 参考系统
高考志愿填报综合参考系统是一个CS模式管理系统,主要包括两大方面,一方面是开发和维护后台数据库,另一方面是前台应用程序的开发．对于前者要求建立起数据一致性和完整性强.数据安全性好的库。而对于后者则要求应用程序功能完备,易使用等特点。具体的来说，我们用微软的 SQL SERVER 2000来作为后台的数据库, SQL SERVER 2000是一个为前台服务的后台开发工具,他提供了多种面向对象的开发工具.特别的是,数据库开发人员能够轻松的进行数据库建立工作。高考志愿填报综合参考系统为用户提供大量的高考信息，包括高校信息，专业信息等等,方便用户快捷查询，测试，找到适合自己的专业。
- 2020-12-05下载
- 积分：1
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GSK980TD串行口通讯软件
用于GSK980TD数控系统的串行口通讯软件，自己用过。还不错。
- 2020-12-07下载
- 积分：1
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基于LabVIEW的QAM调制仿真
本程序在LabVIEW平台上仿真了QAM调制，可以直观的发现噪声对相位的影响。本程序需要LabVIEW8.6以上版本，需要安装调制工具包。
- 2020-11-28下载
- 积分：1
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【基于51单片机】电动车智能充电桩（全套）
实现刷卡充电，远程访问控制等功能。led显示电车电压，电流，功耗，剩余充电时间等。
- 2020-11-02下载
- 积分：1
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中文短文本情感分析语料 外卖评价
短文本情感分析语料,某外卖平台收集的用户评价,正负各8000条,共16000条
- 2020-12-03下载
- 积分：1
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winhex 模板
一共所括102个模板文件AFP_Structured_Fields.tplBMP.tplBoot Sector FAT.tplBoot Sector FAT32.tplBoot Sector NTFS.tplCDFS Directory Entry Ascii.tplCDFS Directory Entry Unicode.tplCDFS Path Tables Ascii.tplCDFS Path Tables Unicode.tplCDFS Volume Descriptor.tplCDFS路径表.tplDalet BWF file header.txtDalet
- 2020-12-05下载
- 积分：1
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算法作业维诺图，有界面有文档
基于Qt开发的维诺图实现，动态界面展示，有PPT有注释。In mathematics, a Voronoi diagram is a way of dividing space into a number of regions.
- 2020-12-02下载
- 积分：1
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PCIe基础文档，部分代码（不是工程）
学习PCIe有一段时间了，这里将这段时间的学习做一个总结。由于手里没有包含PCIe的板子，因此所做的也就是尽力将XILINX提供的实例工程中的关键模块进行分析，包括 PIO_RX_ENGINE.v，PIO_TX_ENGINE.v，PIO_EP_MEM_ACCESS.v ，希望对和我一样的初学者有所帮助。
- 2020-06-25下载
- 积分：1
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verilog_IEEE官方标准手册-2005_IEEE_P1364
The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group
- 2020-12-11下载
- 积分：1
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AD7091R DA转换的FPGA驱动程序
AD7091R DA转换的FPGA驱动程序
- 2020-12-10下载
- 积分：1
