MicroElectronic Circuit Design
微电子电路设计第五版,Richard C. Jaeger, Traveis N. Blalock编著。FIETH EDITIONMICROELECTRONICHM-M- CIRCUIT DESIGNRICHARD C. JAEGERAuburn UniversityTRAVIS N. BLALOCKUniversity of VirginiaMcGrawEducationGrawEducationMICROELECTRONIC CIRCUIT DESIGN. FIFTH EDITIOPublished by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121 CopyrightC 2016 by McGraw-Hill EducationAll rights reserved. Printed in the United States of America. Previous editions 2011, 2008, and 2004. No part of thispublication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system,without the prior written consent of McGraw-Hill Education, including, but not limited to, in any network or otherelectronic storage or transmission, or broadcast for distance learninSome ancillaries, including electronic and print components, may not be available to customers outside the United StatesThis book is printed on acid-free pape1234567890DOw/DOw1098765ISBN978-0-07-352960-8MHID0-07-352960-5sident Products markets Kurt LVice President, General Manager, Products Markets: Marty Langece President, Content Design Delivery: Kimberly Meriwether DavidManaging director: Thomas TimpGlobal Publisher Raghu srinivasanDirector. Prodrelopment: RoDirector, Digital Content Development: Thomas Scaife, Ph DProduct develoVincent brashMarketing manager: Nick Mc faddenDirector, Content Design Delivery: Linda avenariusProgram meSchillingContent Project Managers: Jane Mohr, Tammy Juran, and Sandra M. SchneeBuyer: Jennifer PickelDesign: Studio Montage, St Louis, MOContent Licensing Specialist: DeAnna DausenerCompositor: MPS LimitedPrinter.R. DonnellAll credits appearing on page or at the end of the book are considered to be an extension of the copyright pageLibrary of Congress Cataloging-in-Publication DataJaeger. Richard cMicroelectronic circuit design/Richard C. Jaeger, Auburn University,Travis N. Blalock, University of Virginia. --Fifth editionpages cmIncludes bibliographical references and indexISBN978-0-07-352960-8(alk. paper)-ISBN0-07-338045-8(alk. paper)d 1. Integrated circuits--Design and construction. 2. Semiconductors--Design and construction. 3. Electronic circuitesign. I. Blalock, Travis N. Il. TitleTK7874.J3332015621.3815-dc232014040020The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does not indicatean endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not guarantee the accuracy ofthe information presented at these siteswww.mhhe.comTOTo Joan, my loving wife and life long partnerRichard C. JaegerIn memory of my father, Professor Theron vaughnBlalock, an inspiration to me and to the countlessstudents whom he mentored both in electronicdesign and in life.Travis n blalockBRIEF CONTENTSPreface xxChapter-by-Chapter Summary XXV12 Operational Amplifier Applications 685PART ONE13 Small-Signal Modeling and LinearSOLID-STATE ELECTRONICS AND DEVICESAmplification 77014 Single-Transistor Amplifiers 8411 Introduction to Electronics 32 Solid-State Electronics 4115 Differential Amplifiers and Operational Amplifier3 Solid-state Diodes and Diode circuits 72Design 9524 Field-Effect Transistors 14416 Analog Integrated Circuit Design Techniques 10315 Bipolar Junction Transistors 21517 Amplifier Frequency Response 111318 Transistor Feedback Amplifiers andPART TWOOscillators 1217DIGITAL ELECTRONICSAPPENDICES6 Introduction to Digital Electronics 2837 Complementary MOS (CMOS) Logic Design 359A Standard Discrete Component Values 12918 MOS Memory Circuits 414B Solid-State Device Models and sPIce simulationParameters 12949 Bipolar Logic Circuits 455C TWo-Port Review 1299PART THREIndex 1303ANALOG ELECTRONICS10 Analog Systems and Ideal OperationalAmplifiers 51711 Nonideal Operational Amplifiers and FeedbackAmplifier Stability 587CONTENTSPreface xxCHAPTER 2Chapter-by-Chapter Summary XXVSOLID-STATE ELECTRONICS 41PART ONE2.1 Solid-State Electronic materials 432.2 Covalent bond model 44SOLID-STATE ELECTRONICS2.3 Drift Currents and mobility inAND DEVICES 1Semiconductors 472.3.1 Drift Currents 47CHAPTER 12.3.2 Mobility 48INTRODUCTION TO ELECTRONICS 32.3.3 Velocity Saturation 482.4 Resistivity of Intrinsic Silicon 491.1 A Brief History of Electronics: From2.5 Impurities in Semiconductors 50Vacuum Tubes to Giga-Scale Integration 52.5.1 Donor Impurities in silicon 511.2 Classification of Electronic Signals 82.5.2 Acceptor Impurities in Silicon 511.2.1 Digital signals 92.6 Electron and hole concentrations in1.2.2 Analog Signals 9Doped semiconductors 511.2.3 A/D and D/A Converters--Bridging2.6.1Type Material (ND >NA)52the analog and Digital2.6.2 p-Type Material (N,A>ND)53Domains 102.7 Mobility and Resistivity in Doped1.3 Notational conventions 12Semiconductors 541.4 Problem-Solving Approach 132.8 Diffusion currents 581.5 Important Concepts from Circuit2. 9 Total Current 59Theory 152.10 Energy Band Model 601.5.1 Voltage and current Division 152.10.1 Electron-Hole pair generation in1.5.2 Thevenin and norton circuitan intrinsic semiconductor 60Representations 162.10.2 Energy Band Model for a Doped1.6 Frequency Spectrum of ElectronicSemiconductor 61Signals 212.10.3 Compensated semiconductors 611.7 Amplifiers 222.11 Overview of Integrated circuit1.7.1 Ideal operational amplifiers 23Fabrication 631.7.2 Amplifier Frequency Response 25Summary 661.8 Element Variations in Circuit Design 26Key Terms 671.8.1 Mathematical modeling ofReference 68Tolerances 26Additional Reading 681.8.2 Worst-Case Analysis 27Problems 688.3 Monte Carlo analysis 291.8.4 Temperature Coefficients 32CHAPTER 31.9 Numeric Precision 34SOLID-STATE DIODES AND DIODE CIRCUITS 72Summary 34Key Terms 353.1 The pn Junction Diode 73References 363.1.1 pn Junction Electrostatics 73Additional Reading 363.1.2 nternal diode currents 77Problems 363.2 The i-v Characteristics of the diode 78VIllContents3.3 The Diode Equation: A Mathematica3.15 Full-Wave Bridge Rectification 123Model for the diode 803.16 Rectifier Comparison and Design3.4 Diode Characteristics under reverse, ZeroTradeoffs 124and forward bias 833.17 Dynamic Switching Behavior of the Diode 1283.4.1 Reverse bias 833.18 Photo diodes, solar cells, and3. 4.2 Zero bias 83Light-Emitting Diodes 1293.4.3 Forward Bias 843.18.1 Photo diodes and3.5 Diode Temperature Coefficient 86Photodetectors 1293.6 Diodes under reverse bias 863.18.2 Power Generation from Solar Cells 1303.6.1 Saturation Current in real3.18. 3 Light-Emitting Diodes(LEDs)13Diodes 87Summary 1323.6.2 Reverse Breakdown 89Key Terms 1333.6.3 Diode model for the breakdownReference 134Region 90Additional Reading 1343.7 pn Junction Capacitance 90Problems 1343.7.1 Reverse bias 903.7.2 Forward Bias 91CHAPTER 43.8 Schottky Barrier Diode 933.9 Diode SPICE Model and layout 93FIELD-EFFECT TRANSISTORS 1443.9.1 Diode Layout 944.1 Characteristics of the MOS Capacitor 1453.10 Diode Circuit Analysis 954.1.1 Accumulation Region 1463.10.1 Load-Line Analysis 964.1.2 Depletion Region 1473.10.2 Analysis Using the Mathematical4.1.3 Inversion Region 147Model for the diode 974.2 The nmos transistor 1473.10.3 The Ideal diode model 1014.2.1 Qualitative i-v Behavior of the3.10.4 Constant Voltage Drop Model 103NMOS Transistor 1483.10.5 Model Comparison and4.2.2 Triode Region Characteristics ofDiscussion 104the nmos transistor 1493.11 Multiple-Diode Circuits 1054.2.3 On Resistance 1523.12 Analysis of Diodes Operating in the4.2.4 Transconductance 153Breakdown Region 1084.2.5 Saturation of the i-v3.12.1 Load-Line Analysis 108Characteristics 1543.12.2 Analysis with the Piecewise4.2.6 Mathematical model in theLinear model 108Saturation (Pinch-off)3.12.3 Voltage regulation 109Region 1553.12.4 Analysis Including Zener4.2.7 Transconductance in saturation 156Resistance 1104.2.8 Channel-Length Modulation 1563.12.5 Line and Load Regulation 1114.2.9 Transfer characteristics and3.13 Half-Wave Rectifier Circuits 112Depletion-Mode MosFETs 1573.13.1 Half-Wave Rectifier with resistor4.2.10 Body Effect or SubstrateLoad 112Sensitivity 1593.13.2 Rectifier Filter Capacitor 1134.3 PMOS Transistors 1603.13.3 Half-Wave Rectifier with rc load 1144.4 MOSFET Circuit Symbols 1623. 13.4 Ripple Voltage and Conduction4.5 Capacitances in MOS Transistors 165Interval 1154.5.1 NMOs Transistor Capacitances in3.13.5 Diode Current 117the Triode region 1653.13.6 Surge Current 1194.5.2 Capacitances in the Saturation3.13.7 Peak-Inverse-Voltage(PlV)Rating 119Region 1663.13.8 Diode Power Dissipation 1194.5.3 Capacitances in Cutoff 1663.13.9 Half-Wave Rectifier with Negative4.6 MOSFET Modeling in SPICE 167Output Voltage 1204.7 MOS Transistor Scaling 1683.14 Full-Wave Rectifier Circuits 1224.7.1 Drain Current 1693. 14.1 Full-Wave Rectifier with Negative4.7.2 Gate Capacitance 169Output Voltage 1234.7.3 Circuit and power densities 169ContentsIX4.7.4 Power-Delay Product 1705.3 The pnp Transistor 2234.7.5 Cutoff Frequency 1705.4 Equivalent Circuit Representations for the4.7.6 High Field Limitations 171Transport Models 2254.7.7 The unified mos transistor model5.5 The i-v Characteristics of the bipolarIncluding High Field Limitations 172Transistor 2264.7.8 Subthreshold conduction 1735.5.1 Output Characteristics 2264.8 MOs Transistor Fabrication and layout5.5.2 Transfer characteristics 227Design Rules 1745.6 The Operating Regions of the Bipolar4.8.1 Minimum Feature size andTransistor 227Alignment Tolerance 1745.7 Transport Model Simplifications 2284.8.2 Mos Transistor Layout 1745.7.1 Simplified Model for the Cutoff4.9 Biasing the NMOS Field-EffectRegion 229Transistor 1785.7.2 Model Simplifications for the4.9.1 Why Do We Need Bias? 178Forward-Active Region 2314.9.2 Four-Resistor Biasing 1805.7.3 Diodes in Bipolar Integrated4.9.3 Constant Gate-Source VoltageCircuits 237Bias 1845.7.4 Simplified Model for the4.9.4 Graphical analysis for theReverse-Active Region 238Q-Point 1845.7.5 Modeling Operation in the4.9.5 Analysis Including Body Effect 184Saturation Region 2404.9.6 Analysis Using the Unified5.8 Nonideal Behavior of the bipolarModel 187Transistor 2434.10 Biasing the PMos Field-Effect Transistor 1885.8.1 Junction Breakdown Voltages 2444.11 The junction Field-Effect Transistor5.8.2 Minority-Carrier Transport in theUFET190Base Region 2444.11.1 The JFET With Bias Applied 195.8.3 Base Transit time 2454.11.2 JFET Channel with Drain-Source5.8.4 Diffusion Capacitance 247Bias 1935.8.5 Frequency Dependence of the4.11.3 n-Channel jfet i-v Characteristics 193Common-Emitter current gain 2484.11.4 The p-Channel JFET 1955.8.6 The Early Effect and Early4.11.5 Circuit Symbols and JFET ModelVoltage 248Summary 1955.8.7 Modeling the Early Effect 2494.11.6 JFET Capacitances 1965.8.8 Origin of the Early Effect 2494.12 JFET Modeling in Spice 1965.9 Transconductance 2504.13 Biasing the JFET and Depletion-Mode5.10 Bipolar Technology and sPiCe Model 251MOSFET 1975.10.1 Qualitative Description 251Summary 2005.10.2 SPICE Model Equations 252Key Terms 2025.10.3 High-Performance BipolarReferences 202Transistors 253Problems 2035.11 Practical bias circuits for the bjt 2545.11.1 Four-Resistor bias network 256CHAPTER 55.11.2 Design Objectives for theBIPOLAR JUNCTION TRANSISTORS 215Four-Resistor bias network 2585.11.3 terative Analysis of the5.1 Physical Structure of the BipolarFour-Resistor bias circuit 262Transistor 2165.12 Tolerances in bias circuits 2625.2 The Transport Model for the npn5. 12.1 Worst-Case Analysis 263Transistor 2175. 12.2 Monte Carlo Analysis 2655.2.1 Forward Characteristics 218Summary 2685.2.2 Reverse Characteristics 220Key Terms 2705.2.3 The Complete Transport ModelReferences 270Equations for Arbitrary BiasProblems 271Conditions 221
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物流网络选址与路径优化问题的模型与启发式解法
物流网络选址与路径优化问题的模型与启发式解法120交通运输工程学报2006年(i∈T)(10表1小规模问题的计算结果Tab. 1 Computation result of smalF-scaled problem(xh+xbk)-z≤1(i∈T,∈Ck∈K)(11)最优解∈TUC(j∈C问题规模目标值运行时间/s(12)NG= 3, NT=3, Nc= 83885k≤s1(≤c1121=∑体k∈(13NG=3,Nr=3,Nc=10421.221U-U+Nx≤N-1(i,∈S,k∈K)(14)NG=3,Nr=3,Nc=126850580∈TNG=3,NT=3,Nc=148741162000注:Nc为供应商数量,Nr为配送中心数量,Nc为客户数量ba≤B(g∈G)(16用启发式算法求得初期解xi∈/Q1(i,j∈T∪C,k∈K)(17)l0;∈/0,1∈T(18通过交换配送中心间的路径进行第1次解的改善∈/O,1∈T,j∈C)(19)yk∈/0,1(i∈C,k∈K)(20)通过交换同一路径中客户的位置(2-OPT法)进行第2次解的改善式中:G为供应商的集合;T为配送中心的集合;C为客户的集合;K为车辆的集合;Qk为车辆k的最通过交换不同路径中的客户进行第3次解的改善大载质量:S为C的部分集合;C为从点到点j的距离;B为供应商g的最大供应量;V为配送中心SA模块的最大货物通过量;D,为客户j的需求量;H2为配送中心i的固定费用;L为从供应商g到配送中是否满足终止条件心i的单位运输费用;Fk为车辆k的固定费用;a为解的输出与通过量有关的系数;xk为对于车辆k,如果点i以后的访问点是点j,即为1,否则为0;y为如果点j图1基于SA的混合启发式算法的货物由车辆k配送,即为1,否则为0;v;为如果FiMixed heuristic algorit hm based on sa使用配送中心i,即为1,否则为0;z为如果客户j传统启发式算法与智能启发式算法相结合的混合算由配送中心提供服务,即为1,否则为0;pa为从供法,以期在短时间内求得全局最优解应商g到配送中心的供应量。其中x、3计算分析和pg为决策变量。2问题的求解为了对SA的参数进行设定,进行了预备实验并确定参数如下:初始温度To为200冷却率α为为了验证上述数学模型的正确性,用数理规划07,与温度相关的循环次数调整参数β为.1,最商用软件 LINGO8.0对小规模问题进行了数值计大循环次数将按照问题规模的大小做适当的设定,算,结果见表1。可以看出,随着问题的规模扩大,数据采用人工生成数据,在200km×200km的区计算时间急剧增加;当客户达到14个时,计算时间域内随机生成指定个数的供应商、配送中心和客户,长达45h,显然无法满足解决现实问题的需要。为并生成距离矩阵和客户需求量;采用C语言编程,了满足解决现实问题的需要,有必要开发岀一种能计算结果见表2。从表2中的结果比较可以看出,够在合理的时间内求得准最优解的近似算法。表2最优解与近似解比较传统启发式算法能够在短时间内求得局部最优Tab 2 Comparison of optimal solution and approxi mate solution解,但往往容易陷于局部最优,而无法求得全局最优最优解近似解问题规模解。智能启发式算法能够求得全局最优解,但计算时目标值运行时间/s目标值运行时间/s%间相对较长。如果能够将两者结合起来,既可以防止N=3N=3,Nc=838533965求解过程陷于局部搜索无法跳出,保证全局解的搜3N=3NG=10+2122112100索,又可以缩短搜索时间达到在短时间内求得全局N-3-3Nc12|60s0620110最优解的目的。基于上述考虑本文提出了图1的将ublishrigfoustAingnsestrvcu,trttp/www.urrhi.rctNG=3,Nr=3,Nc=1487411620008895第3期陈松岩,等:物流网络选址与路径优化问题的模型与启发式解法121本算法求得的近似解与 LINGO80计算的最优解心,再从配送中心到客户这一典型的物流过程,涉及之间的误差很小,但计算时间却大大缩短了。依据运输与配送2个阶段和供应商、配送中心和客户3结果虽然无法判定所提岀的混合启发式算法对于大个层次,提出了多供应商、多物流中心情况下的物流规模问题的有效性,但可以看岀,对于求解小规模问路径与配送路径优化问题,给岀了问题的数学模型,题是有效和良好的。对于大规模问题,将利用实例利用传统启发式算法与模拟退火法开发了混合近似进行计算验证。解法,通过人工生成数据和实例计算验证,可以看出4应用实例所提出的数学模型可以准确地描述此类问题,具有良好的适应性,所提出的混合近似解法能够在短时在应用实例中,将港口作为供应商来考虑,以进间内求解问题并得到接近于最优解的近似解,具有口货物从港口经配送中心配送到客户过程中发生的较高的实用价值。但本模型没有考虑库存问题与供费用最小化为目的,以港口的数量和位置、配送中心应商的成本问题,无法达到物流网络中各个环节的数量和位置作为对象进行优化。实例的区域选择山整体优化,有待于今后进一步研究。东省,候选港口为天津港、烟台港、威海港、青岛港参考文献日照港和连云港等6处,候选配送中心设置于山东省除港口城市以外的13个地级市,设定客户分别位References于90个县(包括县级市)。为了分析候选港口和配1 I anen g Flpo C. Spatial de composit ion for a multI送中心的数量及位置与目标值之间的关系,在计算of Production Economics, 2000, 64(1/2/3): 177186过程中,候选港口和配送中心的数量分别从1开始(21 Melkote s, Das kin m s. a n in te grated model of facil ity loca tion增加(港口的位置为随机选择),计算结果见图2、3and transportat ion netw ork design[ J. Transport ation Research part A,2001,35(6):5155386[3] Goets chalckx M, Vidal C J Dogan K Modeling and design ofglobal logistics s yst ems: a review of integrated strat e gic an dt act ical models and design algorithm s[ J European Journal of005◇◇0◇◇◇◇◇◇◇Operat ional Research, 2002, 143 (1):118135791113[4] H wang H S Design of suppl y chain logist ics sy stem con sider-港口数量配送中心数量ing service level[ J. Computers and Industrial Engineerin g,图2港口数量与图3配送中心数量与2002,43(1/2):283297目标函数值关系目标函数值关系[5] WuT H, Low C, Bai J W. Heurist ic s ol ution s to mu ltt depotFig2 Relation of ob ject value Fig 3 Relation of ob ject valuelocatioN rou tin g pr ob lems[ J]. Computers and Operations Re-and ports numberand changing depots num besearch,2002,29(10):13931415可以看出,随着候选港口数量的增加.目标值呈[6 Syam ss. A model and met hodologies for the locat ion p rob lem下降趋势,说明可供选择的港口越多,求得最优解的with logist ical components[ J]. Computers and Operations Re机会越大,但本例中,当候选港口的数量增加到5个se arch,200)2,29(9):l173-1193时,目标值达到最小(实际被选中的港口为3个);候[7 Amiri A. Designing a distribution network in a suppl y chainsystem[ J]. European Jou rnal of O perat ional Research, 2004选配送中心数量的变化也呈相同的趋势,当候选配171(2):567576送中心数量达到9个时,目标值达到最小(实际被选8 G ena m, Syarif a. Hybrid genetic algorit hm for mult+ time pe-中的配送中心为8个);本实例的计算时间都在8sriod production/ distribution planning[ J1. Computers and Ir以内,虽然无法判断所求解为最优解,但从计算结果dustrial Engineering, 2005, 48(4): 799809来看,基本接近最优,因此可以认为本算法对于求解9工丰元,潘福全张丽霞等基于交通限制的路网最优路径算大规模问题也是有效和良好的法J.交通运输工程学报,2005,5(1):9295Wang Feng yuan, Pan Fuquan, Zhang Li xia, et al. Opti mal5结语path algorithm of road netw ork with traffic rest riction[ JIJourn al of Traffic and Trans port ation Engin eering, 2005, 5(1)本文将研究范围界定在商品从供应商到配送中9295.(in Ch ineseo1994-2012ChinaacAdemicJournalElectronicPublishingHouse.Allrightsreservedhttp://www.cnki.net
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