PCI Specification 3.0_PCI 3.0 规范
PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0PCI LOCAL BUS SPECIFICATION, REV.3.0ContentsPREFACESPECIFICATION.……13INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)1查音音鲁垂音音13DOCUMENT CONVENTIONS.………14l. INTRODUCTION…151.1. SPECIFICATION CONTENTS······151.2. MOTIVATION……151.3. PCI LOCAL BUS APPLICATIONS1. 4. PCI LOCAL BUS OVERVIEW171.5. PCI LOCAL BUS FEATURES AND BENEFITS……181. 6. ADMINISTRATION…………………202. SIGNAL DEFINITION m...mn.. 212.1 SIGNAL TYPE DEFINITION222.2. PIN FUNCTIONAL GROUPS..…………222.2.1. System Pins……,…,…,,…,…232.2.2. Address and data pins242.2.3. Interface Control Pins........................252.2.4. Arbitration Pins(Bus Masters Only)272.2.5. Error Reporting Pins....垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂272.2.6. Interrupt Pins( Optional)……282.2.7. Additional signals312.2.8.64- Bit bus extension pins( Optiona)…,,……………………………332.2.9. TAG/Boundary scan Pins(Optional).......342. 10. System Management Bus Interface Pins(Optional)352. 3. SIDEBAND SIGNALS362. 4. CENTRAL RESOURCE FUNCTIONS.····:·····.·············363. BUS OPERATION373.1 BUS COMMANDS373.1. Command definition373. 1.2. Command Usage rules393.2. PCI PROTOCOL FUNDAMENTALS423.2.1. Basic Transfer Control····:············.················433.2.2. Addressing.............143.2.3. Byle lane and Byte enable usage……563.2.4. Bus Driving and Turnaround非音垂垂·非573.2.5. Transaction Ordering and posting….583. 2.6. Combining Merging, and Collapsing。。音垂。音62PCI LOCAL BUS SPECIFICATION, REV.3.03.3. BUS TRANSACTIONS……643.3.1. Read transaction……………653.3.2. Write transaction3.3.3. Transaction termination.………….673.4. ARBItRAtION音垂3.4.1. Arbitration Signaling protoco1..…………………893.4.2. Fast Back-to-Back Transactions. .........................................................93.4.3. Arbitration Parking………………………………………93.5 LATENCY953.5.1. Target Latency…….953.5.2. Master Data latency……….….…….,….….…..……..….,983.5.3. Memory Write Maximum Completion Time limit3.5.4. Arbitration Latency3.6. OTHER BUS OPERATIONS……·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非1103.6.1. Device selection…....…,103.6.2. Special cycle...........3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,…1133.6.4. Interrupt acknowledg3.7. ERROR FUNCTIONS春音·。音垂1153.7.. Parity ger1153.7.2. Parity Checking...........………,163.7.3. Address parity errors…...…,…163.7.4.Error Reporting…17173.7.5. Delayed Transactions and Data Parity Errors.......... 203.7.6. Error Recovery.............,213. 8. 64-BIT BUS EXTENSION1233.8.1. Determining bus Width during System initialization.…….…,1263.9.64- BIT ADDRESSING…..…………………………………………1273.10SPECIAL DESIGN CONSIDERATIONS.1304. ELECTRICAL SPECIFICATION.. m.m.9.1374.1. OVERVIEW…1374.1.1. Transition Road Map……1374.1.2. Dynamic vs Static Drive specificalion…1384.2. COMPONENT SPECIFICATION.……,………………,1…………………1394.2.1. 5V Signaling environment1404.2.2. 33V Signaling environment鲁鲁·垂垂1464.2.3. Timing specification1504.2.4.1determinate Inputs and metastable作,…………1554.2.5. Vendor provided specification..,..…,.…………….………17564.2.6. Pinout recommendation157PCI LOCAL BUS SPECIFICATION. REV.3.04.3. SYSTEM BOARD SPECIFICATION.………1584.3.1. Clock skew,…………………1584.3.2.R··1584.3.3. Pull-ups:····.················:·····…1614.3.4Power1634.3.5. System Timing Budget. ...........1644.3.6. Physical requirements............………674.3.7. Connector Pin assignments……/6844. ADD-IN CARD SPECIFICATION1714.4.1.Add- in Card Pin Assignment..,.,.,………………,1714.4.2. Power Requirements….,.,.,.,.,.,.,,.….,764.4.3. Physical requirements.........1785. MECHANICAL SPECIFICATION1815.1. OVERVIEW1812. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........1825.3. CONNECTOR PHYSICAL DESCRIPTION…………………1954. CONNECTOR PHYSICAL REQUIREMENTS. ...............................2055. CONNECTOR PERFORMANCE SPECIFICATION……………,…2066. SYSTEM BOARD IMPLEMENTATION……………2076. CONFIGURATION SPACEb●看●鲁D鲁0e●2136. 1. CONFIGURATION SPACE ORGANIZATION音垂垂D·垂看垂…2136.2. CONFIGURATION SPACE FUNCTIONS .......................2166.2.1. Device ldentification鲁垂垂2166.2.2. Device Control鲁着鲁D垂2176.2.3. Device status2196. 2.4. Miscellaneous registers·······:········:···:·:··:·:······:··············4······:····2216.2.5. Base addresses……………………….22463. PCI EXPANSION ROMS2286.4. VITAL PRODUCT DATA.2296.5. DEVICE DRIVERS2296.6. SYSTEM RESET.…………………………2306.7. CAPABILITIES LIST2308. MESSAGE SIGNALED INTERRUPTS ...................................................................2316.8.1. MSI Capability Structure..............2326.8.2. MSl-X Capability and Table structures……………….……..2386.8.3. MSI and Msi-X Operation2467. 66 MHZ PCI SPECIFICATION2557. 1. INTRODUCTION2557.2. SCOPE7. 3. DEVICE IMPI TION CONSIDERATIONS7.3.1. Configuration space.......2557. 4. AGENT ARCHITECTURE256PCI LOCAL BUS SPECIFICATION, REV.3.07.5. PROTOCOL.……2567.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,2567.52Latency..-..-.-2577.6. ELECTRICAL SPECIFICATION……………2577.6.. Overview·.·······.··2577.6.2. Transition roadmap to 66 MHz PCI··········.2577.6.3. Signaling Environment.......... 2587.6.4. Timing specification.……2597.6.5. Vendor provided specification. 26.57.6.6. Recommendations·.·························:············:······:········.:··········2657.7. SYSTEM BOARD SPECIFICATION.………,…,……………2667.7.1. Clock Uncertainty ......2667.7.2. Reset2677.7.3. Pullups..2677.7.4. Power..······.·.·::·····布鲁····音D鲁番。是。音垂看····非D∴2677.7.5. System Timing Budget7.7.6. Physical requirements2687.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,2697.8. ADD-IN CARD SPECIFICATIONS春音·。音垂2698. SYSTEM SUPPORT FOR SMBUSn2718. 1. SMBUS SYSTEM REQUIREMENTS2718.1.1. Power………278. 2. Physical and Logical sMBi27l8.1.3. Bus connectivit2728.1.4. Master and slave support....….….…..…..…..,2738.1.5. Addressing and Configuration2738.1.6.Ele2748.1.7. SMBus behavior on Pcl reset.........................2748.2.ADD- IN CARD SMBUS REQUIREMENTS…………2758.2.7Connection2758.2.2. Master and Slave Support...,.…..…….…,...….,2758.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,2758. 2. 4. Power2758. 2.5. Electrical.········.····························275A. SPECIAL CYCLE MESSAGES●鲁●e鲁277A 1. MESSAGE ENCODINGS277A,2. USE OF SPECIFIC ENCODINGS ................................................277B. STATE MACHINES279B. 1. TARGET LOCK MACHINE·;.···.:..···:...···:··.·:····281B.2. MASTER SEQUENCER MACHINE283B 3. MASTER6PCI LOCAL BUS SPECIFICATION. REV.3.0C. OPERATING RULES289C 1. WHEN SIGNALS ARE STABLE..·····.:·.·.::···:·;289C.2. MASTER SIGNALS…音·。·看290C.3. TARGET SIGNALS…291C.4. DATA PHASES…292C.5. ARBITRATION.……………………………………292C.6. LATeNCY······:“·······293C.7. DEVICE SELECTION……………,……………………………293C 8. PARITY垂垂垂D·垂294D. CLASS CODESD 1. BASE CLASS OOH...w.w...296D 2. BASE CLASS OlH296D. 3. BASE CLASS O2H··297D 4. BASE CLASS O3H297D.5. BASE CLASS04H.………………………298D. 6. BASE CLASS OSH298D.7. BASE CLASS06H...………….…………………299D 8. BASE CLASS OZH,300D 9. BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510
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matlab 实现线性调频信号以及分析处理
里面有关于实现matlab的算法以及分析处理山国科技记文在线分布的时频平面作直线积分投影的变换,统称对信号作变换在分布的时频平面里惯用轴的截距和斜率为参数表小直线。因此,当需要沿作直线积分时,可将积分路径(直线)的参数(u,a)替换成()日两对参数之间的关系为:m=-cot,w=! sina。若求信号的变换,并以参数表示积分路径,则有:D.a=PQ线w, (t, wB u-u du∫r(,n)ma(w-mn-m)nh∫m(,w[一(m+motcw lt, wo +mt dt/sinaWo=u/sina上式表明,若是参数为和的信号,则积分值最大;而当参数偏离与或时,积分值迅速减小,即对‘定的信号,其变换会在对应的参数处呈现尖峰。我们自然会想到:多分量的信号的特性在平面里更加突出。即表现为各个尖峰,因而更有利于区别交叉项和噪声。利用变换一定能够获得更好的性能。作为时频分析方法之一,分数阶傅里叶变换ˉ与分布()变换()分别有着一定的数学关系,借助它们的联系,可进一步说明分数阶傅里叶变换的物理意义。信号的分布函数的定义为t+=xtde作为能量型时频表示满足许多期望的数学性质,这里给出其边缘特性X tt wdvXw=wtwat对WD旋转C角度,即对分布实施变换,其结果是RWIW=∫f山国技记文在线而信号的阶分薮阶傅里叶变换X。t的就是将信号的旋转c角度,即对于分数阶傅里叶变换只有旋转不变性,所以有X u= wtP可以看出,对时间轴与频率轴的积分分别是信号在时刻的瞬时功率和信号在频率的谱密度,而信号的对与时间成c角度的轴的积分投影对应着角度为a的分数阶傅里叶变换的幅度平方,这进步从能量的角度说明分数阶傅里叶变换作为广义傅里叶变换的含义。正弦信号在时频平面是一条平行于时间轴的直线,即它的频率不随时间变化,可视为旋转角度为°的完全时间域表示;冲击朕数在时频平面是一条平行于频率轴的直线可视为旋转角度为°的完全频率域表示;信号在时频平面是一条斜率为调频率的直线,当该信号的某一角度的分数阶傅里叶变换与其调频率一致时,在无限长度的理想情况下,表现为幅度为无穷大的冲击,在信号长度有限的情况下,其分数阶傅里卟变换呈现极大值这就是信号在分数阶傅里叶变换域的特点。离散 Chirp fourier变换是最近提出的一种有效的线性调频信号检测技术,它 Fourier变换的一种推广形式,可同时匹配 chirp信号的中心频率和调频率。本文利用修正离散Chirp- Fourie交换( MDCFT)实现干扰信号的检测和参数估计,从而实现对干扰的自适应抑制。分析和仿真表明,该方法可对FM干扰有着极好的抑制效果;同时,由于 Chirp- Fourie变换是维的线性变换,可借助快速傅里叶变换(FFT〕实现,与基于WVD的算法相比,不仅避免了交叉项十扰,而且降低了计算的复杂度,其实现更为简使3.基于Mat1ab的上机仿真过程及结果分析3.1对单分量信号的仿真及结果分析():输入解析信号为x()=eb的分布:40,图单分量信号的分布山国科技论文在线在上述解析信号中加入噪声后,用分布分析其性能图加入噪声的单分量信号的分布由图可以看出实际结果与前面的理论推导致。在实际应用中,信号长度总是有限长的,此时分布呈背鳍状。由图可以得到变换对噪声不太敏感,时频变换后信噪比较高。但当干扰的幅度大到一定程度时,变换的结果会严重变差,甚至分析不出结果。():前两个图是输入解析信号为x(t)=em的变换,后两个图是在这个解析信号中加入噪声以后用变换对其进行的分析:400C501m01501020100150图单分量信号的变换由理论分析可知,当旋转角度与线性调频信号的斜率相這应时,变换将出现一个峰值。这个分析在图中得到了证实。():图前两个图是输入解析信号为x()=e的分数阶傅里叶变换,后两个图是在山国科技论文在线这个解析信号中加入噪声以后用分数阶傅甲叶变换对其进行的分析:分数阶傅甲叶变换变换与变换的紧密联系在图和图的仿真中也可以得到证实HOD50图单分量信号的分数阶傅里叶变换():图的前两个图是输入中心频率是,调频率是的单分量线性调频信号后的Chirp- Fourier变换,后两个图是在这个信号中加入噪声以后用 Chirp-Fourier变换对其进行的分析。通过这个仿真,还将证明一个重要性质: Chirp- Fourier变换可同时匹配线性调频信号的中心频率和调频率的82a图单分量信号的 Chirp fourier变换比较结论:从以上几个仿真图形可以看出,对单分量的信号而言,上述几个变换山国科技论文在线都有非常好的时频聚集性,特别是分布与理论结果完仝一致。在抗噪声方面,对比几个图可知,变换和 Chirp- Fourier变换要比分布和分数阶傅里叶变换吏好。而对于分数阶傅里叶变换和分布,分数阶傅里叶变换的抗噪声性能要好3.2对多分量信号的仿真及结果分析个多分量的线性调频信号的D15020心Dm图多分量信号的一个多分量的线性调频信号的变换50.540多分量信号的变换山国科技论文在线个多分量的线性调频信号的分数阶傅甲叶变换:图多分量信号的分数阶傅里叶变换个多分量的线性调频信号(含两个分量,中心频率和调频率分别为k=)的 Chirp- Fourier变换50299,Q图多分量信号的 Chirp-fourier变换比较结论:从以上四个图可以看出,对于多分量信号,分布由于存在交叉项,时频面模糊不清,而其他三种变换则可以检测到两个信号。从图中还可以看到,Chirp- Fourier变换的效果是最好的。而且我们从图中还可以清楚地看到线性调频信号的中心频率和调频率。4LFM信号的应用线性词频)信号广泛地应用于雷达、声纳和通信等信息系统中。在这类系统中,信号的检测与参数估计是个重要的研究课题,受到特别的关注。下面给出一个基于FRT的MTD雷达信号处理过程的防真实例。假设有一个运动目标,回波信号为Stjn∫t-jwt+nt,其中nt为杂波信号,信号参数为nt是均值为零,方差为的高斯白噪声,信噪比为,观测时间为,采样频率为采样点数为N采用分数阶域的扫描上算法对该冋波信号作计算机仿真,仿真结果如图所从图中可以清楚看到一个LFM信号的存在,而闬目标的峰值非常突出,受杂波的影响相对较小。因此采用FRT的MTD雷达的抗干扰能力较强。另外由于日标的特征非常明显,可以通过适当提高杂波门限的方法来减小虚警概率山国科技论文在线图基于ⅣRFT的MTD雷达信号处理过程的防真5结束语非平稳信号是现代信号处理的主要研究对象之一,对其有很多种理论分析方法。本文介绍的分布,变换,分数阶傅里叶变换,变换是其中比较常用和重要的几种。本文对这几种变换做了初步的介绍,进而对它们进行了一些比较这有助于进一步了解各种变换的性能和作信号分析时选择合适的变换。时频分布之所以受到很多研究人员和信号处理领域的工程人员的重视,是因为它有很多传统傅立叶变换所不具备的性质。由时频分析的定义可知时频表示能给出信号在时域和频域的信息。经过儿年的发展,时频分析理论趋于成熟,并遂渐在实际应用中崭露头角,近年来已在实际的非平稳信号处理中获得了十分广泛的应用。如:信号检测与分类,吋频域滤波,信号综合,系统辩识和谱估计等。在的期刊和国际会议上发表的与采用时频工具处理非平稳干扰有关的论文及研究报告共有余篇,其中以美国大学教授的成果最为显著。时频分析是一个前景很广阔的研究方向,虽然取得了一定的成就,但理论体系尚不十分完备,需要进一步的发展。参考文献[1ˉ张贤达,保铮《非平稳信号分析与处理》[M1998年9月第1版国防工业出版社[2ˉ沈民奋,孙丽莎《现代随机信号与系统分析》M年月第版科学出版社[3丁凤芹,曹家麟《基丁分数阶傅里叶变换的多分量 Chirp信号的检测与参数估计》《语音技术》2004年第1期[4_孙泓波,郭欣,顾红,苏上民,刘国岁《修正 Chirp- Flourier变换及其在SAR运动目标检测中的应用》《电子学报》2003年第1期山国技记文在线[5董永强,陶然,思永,王越《基丁分数阶傅里叶变换的SAR运动目标检测与成像》《兵工学报》1999年第2期L6_陶然,齐林,王越《分数阶 Fourier变奂的原理与应用》LM」2004年8月第1版清华大学出版社[7董永强,陶然,周思永,王越《含未知参数的多分量 chirp信号的分数阶傅里叶分析》《北京理工大学学报》1999年第5期[8ˉ陈辉,王永良《利用离散 Chirp- Flourier变换技术估计调频信号参数》《空军雷达学院学报》2001年第1期[9ˉ齐林,穆晓敏,朱春华《系统中基于 Chirp- Fourier变换的扫频干扰抑制算》《电讯技术》年第期[10]李勇,徐震等《 MATLAB辅助现代工程数字信号处理》[M2002年10月鷥1版西安电子科技人学出版社「111胡昌华,周淘,夏启兵,张伟《基于 MATLAB的系统分析与设计—时频分析》「M12001年7月第1[2]干小宁,许家栋《离散调频-傅里叶变换及其作雷达成像中的应用》《系统工稈与电子技术》2002年第3期
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